Abstract: A semiconductor device comprising a leadframe (4) with a carrier pad (3) bonded thereto, and a die (2) bonded to the carrier pad (3) to form a bonded assembly (5) which is encapsulated in a housing (7) with leads (8) of the leadframe (4) extending therefrom is formed by initially bonding the carrier pad (3) which is pre-coated with a thermosetting first adhesive (20) to the leadframe (4). The first adhesive (20) is raised to its thermosetting cure temperature for bonding the carrier pad (3) to the leadframe (4) by heating the leadframe (4) to a temperature just above the thermosetting cure temperature of the first adhesive (20). A thermosetting second adhesive (22) which is liquid at room temperature is applied to a second major surface (19) of the carrier pad (3), and the die (2) is placed on the second adhesive (22) and aligned with the leadframe (4). The second adhesive (22) is raised to its thermosetting cure temperature to bond the die (2) to the carrier pad (3), and in turn form a bonded assembly (5).

Abstract: A DC to DC converter comprising an inductor, first and second electrically controllable switches and a controller, wherein the first electrically controllable switch is interposed between an input node and a first terminal of the inductor and the second electrically controllable switch extends between a second terminal of the inductor and a common node or a ground, and where a first rectifier extends between the common node or ground and the terminal of the inductor and a second rectifier connects the second terminal of the inductor to an output node, wherein the controller controls the operation of the first and second switches to perform voltage step down or step up, as appropriate, to achieve a desired output voltage and wherein a decision about when to switch the first electrically controlled switch is made as a first function of a voltage error between the output voltage and a target output voltage, and an estimate of the current flowing in the inductor.

Abstract: A circuit for removing non-linearity produced when an amplifier includes a load that results in non-linear current levels is provided. The circuit includes a first transistor element being coupled to one of the differential inputs associated with the amplifier. A second transistor element is coupled to another of the differential inputs associated with the amplifier. The second transistor element is coupled to the current associated with the load. Current passing the collectors of the first and second transistors elements are arranged to be always equal so as to eliminate in the circuit the changes between the base currents of the second transistor element and first transistor element caused by the current associated with the load.

Abstract: A control system may be selectively operated in open loop mode, for example, during data bursts. In a power control system, the transmitted power may be selectively held at a constant level, for example, at the end of a ramp period. The forward path gain of a control system may be varied in an inverse-function manner ahead of an integrator. The slope of a measurement signal from a detector may be made to have a complementary polarity.

Abstract: A system, computer program product and method of obtaining a performance parameter associated with a sensor, such as an accelerometer, is provided. The method includes applying an acceleration to the accelerometer and a first frequency to obtain a sensitivity of the accelerometer at the first frequency. A first self-test is performed on the accelerometer. The first self-test includes stimulating the accelerometer with a first self-test stimulation signal encoded with the first frequency, such that the accelerometer outputs a first signal. A self-test equivalent acceleration is then determined based, at least in part, on the first signal and the accelerometer sensitivity at the first frequency. A second self-test is performed on the accelerometer. The second self-test includes stimulating the accelerometer with a second self-test stimulation signal encoded with the second frequency, such that the accelerometer outputs a second signal.

Abstract: Coil structures and isolators using them. A coil(s) is (are) used as a magnetic field-generating element(s) paired with another coil(s) or other magnetic field-receiving element(s). The coil(s) is(are) formed in or on a substrate which does not include some or all of the driver (i.e., input) or receiver (i.e., output) circuits. The coil(s) and magnetic field-receiving element(s) thus can be manufactured separately from the driver and/or receiver circuitry, using different processes, instead of subjecting the chip areas containing both input and output circuits to post processing to form the coil(s). Isolators can be assembled using such coils with a resultant lower cost. Isolators also can be assembled using transformers made from such coils wherein the transformers can be driven on either of their windings in order to provide bi-directional isolation with a single transformer.

Abstract: The present invention provides a method and apparatus for compensating for temperature effects in the operation of semiconductor processes circuitry, such as reference circuits. The method operates on the realization that the second order effects such as “curvature” in the reference voltage variation over a temperature range is removed. The reference voltage variation over a temperature range can be represented as a straight line. This method provides for the trimming of the absolute voltage by scaling the reference voltage at a first temperature to the desired value by a temperature independent voltage. Then, at a second temperature, the output voltage slope is corrected by adding or subtracting a voltage which is always zero at the first temperature.

Abstract: Transmitter signals are modulated with one or more codes which may represent a pulse even though the code(s) are not shaped as pulses. The code(s) may be generated by defining a pulse by its Fourier components, and then adding random phases to the Fourier components. A time-domain signal may then be created, which may serve as the code to be modulated on a carrier wave. Upon reflection of the transmitter signal, the received signal may be processed by a receiver to recover the pulse. The time-of-flight of the transmitter signal can then be determined, enabling distance measurements to be made.

Abstract: A method of forming a molded sensor includes providing a sensor assembly having a sensor, and a cap coupled to a portion of the sensor, the cap having an opening and forming an interior area. The method also includes blocking the opening in the cap, and molding a moldable material around a portion of the sensor assembly and a portion of a base such that the moldable material is coupled to the sensor assembly and the base, the interior area being substantially free of the moldable material.

Abstract: One or more micromachined (MEMS) switches switch attenuators, such as resistors, into or out of a signal path, such as of a test instrument. The MEMS switches can be fabricated on the same substrate as the attenuators, or the switches or attenuators can be mounted on the same substrate as the others are fabricated. An instrument probe includes attenuators and MEMS switches that are controlled by the instrument and/or by a control circuit in the probe. Optionally, the probe includes reactive elements, such as capacitors, and MEMS switches to compensate for electrical characteristics of the probe and/or probe lead, and the probe or a test instrument automatically sets the MEMS switches to connect appropriate ones of the reactive elements to a signal path within the probe.

Abstract: An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.

Abstract: The application provides a switching circuit for switchably connecting an input node and an output node. The switching circuit comprises a switch operable to switchably connect the input node to the output node in response to a switching signal. A sensor is provided for sensing the voltage between the input and output nodes and providing a sense signal in response thereto. A driver coupled to the sensor adjusts the switching signal in response to the sense signal.

Abstract: Transmitter signals are modulated with one or more codes which may represent a pulse even though the code(s) are not shaped as pulses. The code(s) may be generated by defining a pulse by its Fourier components, and then adding random phases to the Fourier components. A time-domain signal may then be created, which may serve as the code to be modulated on a carrier wave. Upon reflection of the transmitter signal, the received signal may be processed by a receiver to recover the pulse. The time-of-flight of the transmitter signal can then be determined, enabling distance measurements to be made.

Abstract: Versatile control pin electronics are disclosed. The control pin electronics are coupled to a control pin and allow for the passing of both analog and digital control signals. The control pin electronics work with digital logic having logic levels that are compatible with analog signals having predefined voltage and current limits. The versatile control pin electronics include both a voltage regulator that sets a regulated voltage at the control pin and a current limiter. The versatile control pin electronics can be coupled to a comparator to provide both hysteresis and latching functionality from a single pin.

Abstract: An apparatus and method is provided for optimizing LED driver efficiency. The present invention offers low cost solutions for powering LEDs while minimizing overall power dissipation in devices powered by a depletable power source. Low system cost is attained using a charge pump to increase LED drive voltage level and implementing combinations of drive techniques to overcome the inefficiency of the charge pump. A switch bypasses the charge pump when depletable power source output voltage is sufficient to directly drive an LED load. At certain output voltage levels, the switch can be opened causing the charge pump to boost drive voltage. The output voltage may also be PWM modulated to drive the LED load and, at some voltages, the depletable power source may drive the LED load directly. Efficiency levels of 90-97% are attainable.

Abstract: A semiconductor wafer comprises an SOI comprising a device layer on an oxide layer supported on a handle layer. Micro-mirrors are formed in the device layer, and access bores extend through the handle layer and the oxide layer to the micro-mirrors for accommodating optical fibers to the micro-mirrors. The access bores are accurately aligned with the micro-mirrors, and the access bores are accurately formed of circular cross-section. Each access bore comprises a tapered lead-in portion extending to a parallel portion. The diameter of the parallel portion is selected so that the optical fibers are a tight fit therein for securing the optical fibers in alignment with the micro-mirrors. The tapered lead-in portions of the access bores are formed to a first depth by a first dry isotropic etch for accurately forming the taper and the circular cross-section of the tapered lead-in portions.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses; and a multiplexer configured to supply first and second current memory addresses to selected ones of the first and second memory pipelines in response to a control signal.

Abstract: A method of forming a MEMS device provides a wafer having a base with a conductive portion. The wafer also has an intermediate conductive layer. After it provides the wafer, the method adds a diaphragm layer to the wafer. The method removes at least a portion of the intermediate conductive layer to form a cavity between the diaphragm layer and the base. At least a portion of the diaphragm layer is movable relative to the base. After it forms the cavity, the method seals the cavity.

Abstract: A digital controller for use with a full-bridge power converter which includes an isolation transformer that conducts first and second currents of opposite polarity during respective power-transfer phases. A current transformer senses the currents, and a non-zero current Iin is generated when either of the first or second currents is >0. The controller includes a sigma-delta modulator arranged to integrate a current applied to its input and to modulate the integrated signal to a bitstream. Iin is integrated by a first integrator and the bitstream is decimated to a digital word by a first decimation filter during the first power-transfer phase, and is integrated by a second integrator and decimated with a second decimation filter during the second phase. The difference between the digital values is used to adjust the pulses that operate the full-bridge switches as necessary to reduce any imbalance between the first and second currents.

Abstract: Integrated circuit package assemblies and packaging methods are provided. An integrated circuit package assembly includes a first circuit package including a first substrate having a top surface and a bottom surface, a first circuit die containing a programmable processor mounted to and electrically connected to the bottom surface of the first substrate, a bottom connector on the bottom surface of the first substrate and top circuit connections on the top surface of the first substrate, and a second circuit package mounted on the top surface of the first substrate and electrically connected to the top circuit connections of the first circuit package.