Abstract: An output stage interface circuit for interfacing with a data bus, comprising first and second rails for receiving respectively a high voltage and a low voltage from a power supply; a data output terminal; a first main switch element coupled between said terminal and the first rail and comprising a first main MOS device having a gate and an independently configurable back gate, and responsive to a first data control signal applied to the gate pulling the voltage on the data output terminal toward the first rail voltage; and a first control circuit responsive to the voltage on said terminal being pulled from a first state across a first voltage reference to a second state for coupling said back gate to said terminal and permitting coupling of the gate of said MOS device to said terminal, the first main MOS device presenting a high impedance on the terminal when its voltage is pulled to the second state.

Abstract: An automatic gain control circuit is disclosed. The automatic gain control circuit receives a radio frequency signal at an input. The input passes the radio frequency signal to a first gain loop having a changeable gain. A low pass filter filters the radio frequency signal. In a second gain loop, the gain of the filtered signal is adjusted. The automatic gain control circuit includes at least one signal detector for detecting a signal level in the first gain loop and a signal level in the second gain loop. The automatic gain control circuit also includes an adjustment module for adjusting the gain of the first and second gain loops based upon the detected signal levels wherein overall gain of the first and the second gain loops is increased no greater than a predetermined value.

Abstract: An output stage, comprising a first transistor operable to pull a voltage at an output node towards a first voltage, and a rechargeable energy store having a potential difference between first and second terminals wherein the rechargeable energy store is arranged to be controllably connected between the output node and a second voltage supply such that the voltage at the output node can be driven to a voltage outside of a range defined between the first and second voltages.

Abstract: A pseudo-differential active RC integrator is described. The pseudo-differential active RC integrator includes a common-mode feedback sub-circuit to control the common-mode output signal of the integrator. The common-mode feedback subcircuit may be coupled to one or more virtual ground nodes of the pseudo-differential active RC integrator, and may include one or more transconductors.

Abstract: A current-mode instrumentation amplifier (IA) error reduction circuit and method employs a current-mode IA topology and an auto-zero circuit. The IA receives a differential voltage (VINP?VINN) and produces differential DC currents (IDC1, IDC2) in response, which are summed to produce the amplifier's output current. Ideally, when VINP=VINN, IDC1 and IDC2 will be equal; however, due to mismatches an error component Ierror will be present such that IDC1=IDC2±Ierror. The auto-zero circuit is employed to reduce the magnitude of Ierror. In operation, in an ‘auto-zero mode’, VINP and VINN are connected together and the auto-zero circuit operates to make IDC1=IDC2; a voltage needed to effect this is stored. Then, in ‘normal mode’, VINP and VINN are disconnected from each other and the IA is placed in the signal path, with the stored voltage acting to keep the magnitude of Ierror low.

Abstract: A method and apparatus for extending the linear range of a phase detector. In one embodiment, a limited range phase difference is generated between selected edges of first and second input signals, and an excursion of the limited range phase difference beyond a predetermined threshold is detected. In response to detecting the excursion of the limited range phase difference beyond a threshold, an edge of the first or second input signal is prevented from influencing subsequent generation of the limited range phase difference, and a compensated phase difference is generated, derived from the limited range phase difference and including a correction component which compensates for the effect of preventing said edge from influencing subsequent generation of the limited range phase difference.

Abstract: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores.

Abstract: A ?-type voltage-controlled variable attenuator is disclosed. The variable attenuator may include variably resistive components in the series and shunt arms. The variably resistive components may be implemented as field effect transistors. The shunt arms may be coupled to the series arm, and the variable attenuator may lack capacitors between the series arm and shunt arms. The series arm and shunt arms may display variable resistances which, in combination, operate to provide a variable level of attenuation of an input signal. The variable attenuator may provide any level of attenuation of an input signal over a wide frequency range. The variable attenuator may be implemented as an integrated circuit.

Abstract: A die has a part that is sealed with a cap. The seal can be hermetic or non-hermetic. If hermetic, a layer of glass or metal is formed in the surface of the die, and the cap has a layer of glass or metal at a peripheral area so that, when heated, the layers form a hermetic seal. A non-hermetic seal can be formed by bonding a cap with a patterned adhesive. The cap, which can be silicon or can be a metal paddle, is electrically coupled to a fixed voltage to shield the part of the die.

Abstract: A MEMS microphone has a backplate, a diaphragm movable relative to the backplate, and a backside cavity adjacent to the backplate or the diaphragm. The backside cavity has sidewalls with at least one rib protruding inward toward a center of the backside cavity.

Abstract: A digital signal processor includes a control block configured to issue instructions based on a stored program, and a compute array including two or more compute engines configured such that each of the issued instructions executes in successive compute engines of at least a subset of the compute engines at successive times. The digital signal processor may be utilized with a control processor or as a stand-alone processor. The compute array may be configured such that each of the issued instructions flows through successive compute engines of at least a subset of the compute engines at successive times.

Abstract: An IC current reference includes a reference voltage Vref, a current mirror, and a transistor connected between the mirror input and a first I/O pin and which is driven by Vref. A resistor external to the IC and having a resistance R1 is coupled to the first I/O pin such that it conducts a current Iref which is proportional to Vref/R1; use of a low TC/VC resistor enables Iref to be an accurate and stable reference current. The current mirror provides currents which are proportional to Iref, at least one of which is provided at a second I/O pin for use external to the IC. One primary application of the reference current is as part of a regulation circuit for a negative supply voltage channel, which can be implemented with the same number of external components and I/O pins as previous designs, while providing superior performance.

Abstract: A power converter system including an LC oscillator circuit, an oscillator drive circuit for driving the LC oscillator circuit, a rectifier circuit coupled to the LC oscillator circuit for providing a DC output, and a switching circuit for controlling the duty cycle of the oscillator drive circuit to modulate the power in the LC oscillator circuit and the rectifier circuit.

Abstract: An amplifier topology includes an input stage comprising a differential pair which conducts respective output currents in response to a differential input signal. Bias current sources provide the pair's tail current and respective bias currents for the input stage in response to a drive voltage. After flowing through the input stage, most or all of the input stage bias currents are summed at a summing node, the summed currents being a current Isum. The input stage also has a feedback loop which includes a bias generator circuit arranged to receive Isum, and to provide the drive voltage to the bias current sources such that Isum is maintained approximately constant. By so doing, the output impedance of the bias current sources is effectively increased, which serves to improve the amplifier's CMR and PSR characteristics.

Abstract: A single chip integrated circuit measuring circuit (1) for determining a characteristic of the impedance of an external complex impedance circuit (2) for facilitating characterization of the impedance of the complex impedance circuit (2) comprises a signal generating circuit (7) for generating a variable frequency stimulus signal for applying to the complex impedance circuit (2). A first receiving circuit (10) receives a response signal from the complex impedance circuit (2) in response to the stimulus signal and conditions the response signal. A first analog-to-digital converter (68) converts the conditioned response signal to a first digital output signal, which is read from the first analog-to-digital converter (68) through a first digital output port (14). The response signal from the complex impedance circuit (2) is a current signal, and a current to voltage converter circuit (64) converts the response signal to a voltage signal.

Abstract: A bandgap voltage reference circuit with an inherent curvature correction which comprises an amplifier having an inverting terminal, a non-inverting terminal and an output terminal is described. A first and second bipolar transistor operable at different current densities are provided each of the transistors being coupled to a corresponding one of the inverting and non-inverting terminals of the amplifier such that a ?Vbe is reflected across a first load element. A current biasing circuit is provided which includes a semiconductor device coupled to each of the first and second bipolar transistors and is configured for applying a non-linear bias current to the first and second bipolar transistors for biasing thereof.

Abstract: A bandgap reference circuit which is operable in low supply conditions is described. Such a circuit includes a second amplifier and a resistor at the output of a bandgap reference cell to create a constant current summing node at which PTAT and CTAT currents are summed. In modifications to the circuit it is possible to also provide a voltage reference node corresponding to the signal provided at the summing node. A further modification enables generation of a second voltage reference whose value is related to the base emitter voltage Vbe of a bipolar transistor. Further modifications provided for the generation of curvature correction within the circuit by biasing each of the first and second bipolar transistors Q1 and Q2 with currents of different forms.

Abstract: A method and system for determining camera positioning information from an accelerometer mounted on a camera. The accelerometer measures the orientation of the camera with respect to gravity. Orientation measurement allows user interface information to be displayed in a “right side up” orientation on a viewfinder for any camera orientation. Alternatively, an artificial horizon indicator may be displayed in the viewfinder. The accelerometer may also measure camera movement. Camera movement information together with camera orientation can be used to determine camera usage. Additionally, camera movement information can be used to determine a minimum shutter speed for a sharp picture.

Abstract: A power converter provides power across an isolation barrier, such as through the use of coils. A coil driver has transistors connected in a positive feedback configuration and is coupled to a supply voltage in a controlled manner by measuring the output power and opening or closing a switch as needed between the power supply and the coil driver. An output circuit, such as a FET driver, can be used with or without isolation to provide power and a logic signal.

Abstract: A digital filter uses memory to emulate a variable shift register. Data samples are stored in a memory. The data samples are read from the memory, multiplied with corresponding coefficients stored in the same or a different memory, logically shifted, and written back into the memory so as to emulate a variable shift register. The data samples can be logically shifted by one or more bits at a time.