Abstract: A bandgap voltage reference circuit that can be implemented with low noise characteristics is described. To achieve such low noise, a bandgap reference circuit is provided that includes an amplifier coupled at its inputs to first and second transistors respectively, the transistors being arranged to generate a voltage representative of the base emitter voltage differences between each of the first and second transistors across a sensing resistor. The circuit additionally provides an additional current to the sensing resistor to reduce the noise contribution into the amplifier from the first transistor. Such a circuit may be corrected for second order temperature effects by inclusion of a temperature dependent current source.

Abstract: In one aspect, a resistor process invariant transconductor is provided. The transconductor comprises a voltage input configured to receive at least one voltage signal, a current output configured to provide at least one current signal, wherein a ratio between the at least one voltage signal and the least one current signal forms a total transconductance for the transconductor, and a circuit including at least one integrated resistor connected between the voltage input and the current output, the circuit adapted to maintain the total transconductance substantially constant across variation of the at least one integrated resistor.

Abstract: An interface error monitor system for monitoring data exchanged between a controller and a data converter over an interface includes a multi-stage linear feedback shifter register associated with the data converter for generating a pseudo random number sequence; a signature generating circuit responsive to data exchanged between the controller and data converter for altering the pseudo random number sequence generated by the linear feedback shifter register to create a signature of the data.

Abstract: A drive arrangement for a micromachine includes a plurality of fixed electrodes arranged so as to have a common centroid.

Abstract: Methods and an apparatus are provided for interpolation of pixels in a pixel array having rows and columns of pixels. The apparatus includes a shift register array to shift pixel values of the pixel array, the shift register array including two or more shift registers; an interpolation filter array interconnected to the shift register array, the interpolation filter array including one or more interpolation filters; and a controller configured to provide pixel values in columns of the pixel array from the shift register array to respective interpolation filters in a first mode and configured to provide pixel values in rows of the pixel array from the shift register array to respective interpolation filters in a second mode. The controller may be configured to supply vertical sub-pixel values from the shift register array to the interpolation filters to generate diagonal sub-pixel values.

Abstract: In one embodiment, a circuit comprises at least first and second circuit stages, at least one level shifting circuit, and a control circuit. The first circuit stage is configured and arranged to produce a reference voltage at the at least one first output during each first phase of at least first and second phases, and to produce an output signal at the at least one first output that is responsive to an input signal at the at least one first input during each second phase of the at least first and second phases. The at least one level shifting circuit comprises at least one capacitor and at least one switch and is coupled between the first circuit stage and the second circuit stage.

Abstract: In one embodiment, a configurable timing generator outputs at least one timing signal. The configurable timing generator comprises a first timing generator configurable to output the at least one timing signal so that the at least one timing signal is adaptable to a plurality of applications. In one embodiment, a configurable parameter storage unit comprising a parameter storage area configurable so as to store a plurality of parameters at least partially defining a desired plurality of waveform hierarchy elements, where the desired plurality of waveform hierarchy elements enable the definition of a waveform. In one embodiment, a method of constructing a waveform for a configurable timing generator, the method comprising acts of constructing a first pattern waveform, where the first pattern waveform comprises a first basic pulse, and constructing a first sequence waveform, where the first sequence waveform comprises a plurality of repetitions of the first pattern waveform.

Abstract: An input stage receives a differential input signal at first and second input nodes and provides a differential output current at first and second output nodes. The differential output current includes a component taken from the input nodes through first and second impedances, and an additional component generated in response to a sample of the voltage of the differential input signal. A transconductance cell having cross-coupled inputs may generate the additional component of the output current.

Abstract: In one embodiment, a configurable timing generator outputs at least one timing signal. The configurable timing generator comprises a first timing generator configurable to output the at least one timing signal so that the at least one timing signal is adaptable to a plurality of applications. In one embodiment, a configurable parameter storage unit comprising a parameter storage area configurable so as to store a plurality of parameters at least partially defining a desired plurality of waveform hierarchy elements, where the desired plurality of waveform hierarchy elements enable the definition of a waveform. In one embodiment, a method of constructing a waveform for a configurable timing generator, the method comprising acts of constructing a first pattern waveform, where the first pattern waveform comprises a first basic pulse, and constructing a first sequence waveform, where the first sequence waveform comprises a plurality of repetitions of the first pattern waveform.

Abstract: A dual mode comparator circuit is disclosed. The dual mode comparator includes a plurality of differential transistor pairs. Each differential transistor pair includes a plurality of inputs and outputs. The outputs of the differential transistor pairs are coupled to inputs of a multiplexor. The multiplexor includes at least one control input for selecting between the multiplexor inputs and provides the selected input to the multiplexor output. The dual mode comparator further includes a comparator back end that is coupled to the output of the multiplexor. The comparator back end may include a folded cascode and additional gain stages. The comparator back end provides the comparator output to the next stage. The dual mode comparator may be used in automatic testing equipment embodiments.

Abstract: In one aspect, a software application for facilitating design of a register specification is provided. The application comprises an interface adapted to receive input from a user indicating information about at least one register in the register specification, the interface generating register information based on the received input, a translator coupled to the interface to receive the register information and adapted to convert the register information to an internal representation, and at least one filter adapted to transform the internal representation into at least one respective output format.

Abstract: A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.

Abstract: A ghost image cancellation technique for video signals received from multipaths during transmission of a TV signal over a transmission channel. In one example embodiment, an apparatus computes edge parameters of synchronization signals received from each of the multipath video signals. The edge parameters are then used to select an input video signal. The selected input video signal along with the computed edge parameters are then used to remove remaining video signals from the video signals received from the multipaths to cancel ghost images.

Abstract: An analog to digital converter system includes at least one stage for providing a first full precision, full latency output and a second output providing a less than full latency, less than full precision coarse level indicator signal.

Abstract: In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall signal to stall the multi-cycle instruction within one of the stages of the execution pipeline. The MCI controller is adapted to issue a plurality of instructions to subsequent stages in the pipeline while the multi-cycle instruction is stalled.

Abstract: A low-temperature inorganic dielectric ALD film (e.g., Al2O3 and TiO2) is deposited on a packaged or unpackaged chip device so as to coat the device including any exposed electrical contacts. Such a low-temperature ALD film generally can be deposited without damaging the packaged chip device. The ALD film is typically deposited at a sufficient thickness to provide desired qualities (e.g., hermeticity for the entire packaged chip device, passivation for the electrical contacts, biocompatibility, etc.) but still allow for electrical connections to be made to the electrical contacts (e.g., by soldering or otherwise) directly through the ALD film without having to expose the electrical contacts.

Abstract: A method of decoding data comprising a plurality of data-bursts, comprising the steps of: i) receiving a first one of the data-bursts, ii) associating hypothesis data with the or each received data-bursts; iii) attempting to decode the data; and iv) if the decode is successful to power down the receiver, and if the decode is unsuccessful receiving a further one of the data-bursts and repeating steps ii) to iv), until all of the data has been received.

Abstract: A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.

Abstract: A MEMS microphone has a backplate with a given backplate aperture, and a diaphragm having a diaphragm aperture. The given backplate aperture is substantially aligned with the diaphragm aperture.

Abstract: A cross-coupled switched capacitor circuit that has two branches. During a first phase for the first branch, an input voltage is provided that causes charge to move through a resistor and to be placed onto a plate of the capacitor within the branch. An equivalent amount of charge is transferred to an output node. The output node may be a summing node of a sigma-delta modulator. The summing node is one of the inputs to an operational amplifier that is part of the integrator of the sigma-delta modulator. The resistor and the capacitor in the first branch define an RC circuit and corresponding RC time constant. During the first phase, the capacitor does not reach a fully settled voltage for a desired resolution. During the second phase, the capacitor in the first branch of the circuit is set to a defined voltage. The defined voltage may be the settling voltage had the capacitor been allowed to settle during the first phase.