Abstract: A stress relief substrate having a pair of ball grid arrays (BGAs) is interposed between a PC board and an electrical component. The BGAs are electrically connected through vias in the stress relief substrate to connect component circuitry to the PC board. In one embodiment, the BGAs are offset on a flexible substrate so that there is some open space between the edges of electrically connected solder balls. This allows the substrate to warp during thermal cycling and absorb the stress caused by TCE mismatch. In another embodiment, the BGAs are aligned on a rigid substrate that is formed with holes interposed between the solder balls. This reduces the amount of material that interconnects the solder balls so that the substrate tends to flex rather than transfer the TCE stress to the solder balls.

Abstract: Linearized unity-gain folding amplifiers include first and second differential pairs of transistors that have offset voltages between control terminals and first current terminals. The control terminals are differentially coupled through input paths to a differential input port and the joined first current terminals receive respective first and second currents through respective first and second level-shift resistors. Thus, folded and level-shifted signals can be differentially coupled via output paths between the first and second level-shift resistors and an output port. For each of the differential pairs, at least one correction voltage is generated to substantially match the offset voltage of one of the transistors of that differential pair when a differential input voltage has one polarity and the offset voltage of another of the transistors when the differential input voltage has a different polarity.

Abstract: A broadband modem hybrid transformer couples a broadband modem to a plain-old-telephone (POTs) line. The hybrid includes a full bridge having an impedance matching network to reduce the transhybrid attenuation of the hybrid. The second matching network(s) include various resistive and reactive components which together provide an impedance value selected based upon the impedance of the telephone line typically reflected into the primary windings of the transformer. The matching network increases the transhybrid attenuation of the hybrid, and thus reducing the amount of noise which couples from the modem transmit circuit to the modem receive circuit through the hybrid.

Abstract: The current flow from a temperature-variable current source to a Hall-effect element is adjusted according to sensed temperature conditions of the element to compensate for temperature-dependent changes in the magnetic-field sensitivity of the Hall-effect element and in the magnitude of the permanent magnetic fields of magnetic components sensed by the element. A trimmable resistor is connected between two external terminals of a Monolithically integrated circuit to provide external control over the sensitivity of the temperature variable current source to changing temperature conditions. The device also alternately switches the quadrature states of output and bias supply contacts of the Hall-effect element to compensate for the offset and drift thereof.

Abstract: A device for detecting with differential capacitors accelerations in more than one orientation through time-division multiplexing. A micromachined mass is movable along or about any axis in response to a force. The mass forms the common electrode of a set of differential capacitors, wherein the other electrodes of each differential capacitor are fixed. With each differential capacitor, one fixed electrode is set to one voltage and the other fixed electrode is set to a second voltage. The mass is connected to the input of an amplifier and to a switch for connecting the mass to a fixed voltage. The output of the amplifier is coupled to a demodulator for each orientation. A timing circuit activates one demodulator at a time. By toggling the voltages on the fixed electrodes of the differential capacitor corresponding to the active demodulator, the movement of the mass in the orientation corresponding to the active demodulator can be determined.

Abstract: An integrated circuit comprises means responsive to a normally changing signal at an input of the integrated circuit to implement a primary function of the circuit, and means for monitoring this normally changing signal at the input in question of the integrated circuit. This monitoring means is responsive to suspension of the normally changing signal to communicate a signal for implementation of a secondary function of the circuit. In an exemplary embodiment, the invention is directed towards implementation of power-down of the circuit, without using an explicit power-down or reset pin. An input signal which normally changes at minimum rate, e.g. preferably a clock signal, is held in a fixed state for a minimum duration to invoke the reset or power-down mode. An integrated circuit may thus be powered-down or reset where no explicit power-down or reset pin is available.

Abstract: A write channel in read/write disc drive system for writing data signals to a drive includes a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift; and a delay locked loop circuit responsive to the data signal for controlling the delay of the variable circuit.

Abstract: A programmable pulse slimmer system for a low pass ladder filter includes a filter input current source for providing to a low pass ladder filter the input signal to be filtered; and a high frequency boost current source for injecting into the low pass ladder filter forward of the first inductor device a high frequency load current which is a scaled inverse replica of the input signal to provide gain at the high frequency end of the low pass band of the low pass ladder filter.

Abstract: A digital television (DTV) receiver receives a data signal that is divided into a plurality of segments each separated by a known data segment sync sequence. The receiver includes a data segment sync signal detector that receives the data signal and filters the signal to provide a filtered data signal. The detector computes the difference between samples of the filtered data signal and an average expected filtered signal value that is representative of a nominal filtered signal value in the middle of the segment sync sequence. The detector then computes the absolute value of the computed difference, and the resultant absolute value is summed with a sampled value from the previous segment and the summed value is stored into an accumulator. The process is repeated for several segments. The location of the data segment sync sequence within the segment is determined by comparing the summed values to determine the smallest summed value, which represents the center of the segment sync sequence.

Abstract: A progressive-compression logarithmic amplifier, amplifier stage, and method for increasing the bandwidth of a differential-input progressive-compression logarithmic amplifier are disclosed. The amplifier stage provides positive gain increases for decreases in the impedance of the load driven by the stage. When multiple amplifier stages of this type are cascaded, the gain increase in each stage compensates for high-frequency roll-off due to the input capacitance of the following stage. The compensating is activated by the roll-off effect itself, making the device self-compensating. This is preferably accomplished by providing a drive current sensing path that makes each node of the stage's differential output respond in opposition to the drive current drawn at the stage's other differential output--that is, an increase in drive current at one output node drops the voltage at the other output node.

Abstract: An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise.

Abstract: A tri-state input detection circuit produces two binary outputs that indicate whether a tri-state input signal is high, low, or in a hi-impedance state. A pair of transistors conduct a current in response to a tri-state signal presented at an input node. Circuitry is provided to pull the input node to a known voltage when the input signal is in its hi-Z state. The transistors are series-connected to respective current sources, with the junctions between the transistors and their current sources forming the circuit's binary outputs. The output impedances of the current sources are made less than those of their respective transistors, so that when turned on by the input signal, a transistor pulls its associated output high or low. The circuit produces a unique binary output for each of the three input signal states.

Abstract: The chopping frequency driving a chopper-stabilized amplifier (CSA) is dynamically varied between an upper and lower frequency limit to reduce the intermodulation distortion, clock noise and low-frequency noise found in prior art designs. The upper limit is set to accommodate the settling times required by the CSA's memory capacitors, and the lower limit is set to a non-zero frequency significantly greater than DC to reduce low frequency noise. The two limits permit IMD and clock noise to be widely scattered and enable a near optimum trade off between IMD and chopping noise on one hand, and low frequency noise on the other. The chopping frequency is preferably generated digitally with a loadable counter which divides down a fixed frequency master clock, with the binary value presented at the counter's load inputs periodically varied to dynamically vary the division ratio and thus frequency modulate the chopping frequency.

Abstract: A micromachined gyroscope has first and second coplanar bodies suspended over a substrate and movable in their plane relative to the substrate. The first body is dithered along a dither axis and is movable relative to the second body on the dither axis, but is rigidly connected for movement along an axis transverse to the dither axis. The second body is anchored so that it is substantially inhibited from moving along the dither axis, but can move with the first body along the transverse axis. The gyro has stop members and an anti-levitation system for preventing failure.

Abstract: Improved data scramblers and swapper cells and improved digital to analog converters are provided. The improved swapper cells permit data to be propagated through the cell immediately upon receipt. The determination of whether to swap data or pass it directly through is based on a history of data values propagated through the cell, but is independent of the values of the particular inputs being swapped. The data scrambler is structured to permit the possible data inputs on swapper cells in the scrambler to be restricted. A minimum delay data scrambler for use in a fast digital to analog converter is disclosed using these components.

Abstract: Time-delay circuits are realized with first and second capacitors, a differential amplifier, a programmable current source and a differential pair of transistors. The current source directs first and second currents to the first and second capacitors and the differential pair steers a third current of the current source to either selected one of the capacitors to provide charging and discharging currents to the capacitors. The differential amplifier generates a delayed output pulse in response to voltages of the first and second capacitors. The capacitors are preferably formed by the interconnection system of an integrated circuit, i.e., the metallic circuit paths that are typically carried on an integrated-circuit substrate. N+1 of the delay circuits are combined with a phase comparator to form an interpolator that responds to an input data pulse by generating N output data pulses that span a period between the input data pulse and a successive input data pulse.

Abstract: Comparator structures are shown which improve latching accuracy and enhance bandwidth for operations such as high-speed sampling in a variety of applications (e.g., analog-to-digital converters and automatic test equipment). The structures include an input differential pair of transistors having first and second control structures, a differential output amplifier and a clamp that limits the signal level of at least one of the first and second control structures. The clamp includes first and second Schottky diodes that are oppositely oriented and coupled between the first and second control structures. Altenatively one side of the diodes can be coupled to bias structures that respond to a threshold signal. Bias networks respond to a sampling threshold signal and stabilize biases in the input differential pair and the differential output amplifier.

Abstract: An RF mixer provides extended dynamic range with reduced noise by utilizing degeneration inductors in the RF input section of a doubly balanced mixer. Degeneration inductors are also utilized in a mixer having a class AB input section. A current mirror in the class AB input section is also inductively degenerated for further noise reduction. The input section is biased by an all-NPN bandgap reference cell which is tightly integrated into the input section so as to reduce the power supply voltage required for the reference cell. The mixer can be optimized for wide input voltage ranges or low distortion.

Abstract: A circuit that produces a gate drive voltage for a MOS transistor switch, that receives an input voltage "on" a source terminal, includes a first input that receives the input voltage, a second input that receives a bias voltage, and a voltage storage element. A first switch connects the voltage storage element to sample one of the input voltage and the bias voltage during a first of first and second non-overlapping time intervals. A second switch connects the voltage storage element to increase the sampled voltage by another of the input voltage and the bias voltage to the gate drive voltage during the second non-overlapping time interval, while maintaining the gate drive voltage less than a breakdown voltage of the MOS transistor switch. A third switch connects the voltage storage element to provide the gate drive voltage to the MOS transistor switch such that a gate-to-source voltage of the MOS transistor switch is maintained approximately constant.

Abstract: A method and system for providing adaptive filtering in a communication system. The method and system modify coefficients of a finite impulse response filter fed by a sequence of digital samples in accordance with an error signal in floating point format. The floating point error signal includes only a sign bit and an exponent term. The exponent term is added to an exponent term of an adaptation coefficient to produce a composite error signal. The adaptive filter is used as a linear adaptive equalizer and as an echo canceler.