Abstract: An interpolator utilizes two ranks of transistors to generate a plurality of interpolator currents within the confines of a low power supply voltage. The first rank of transistors are underdriven, thereby generating a plurality of partially switched currents having shallow Gaussian-shaped functions. The partially switched currents are then spatially amplified by the second rank of transistors to reduce the overlap of the currents from adjacent transistors. The first rank of transistors are driven ratiometrically by the difference of two control currents, thereby eliminating errors caused by inaccurate resistors and current sources. A biasing op-amp senses the interpolator currents and servos the first rank of transistors, thereby regulating the interpolator currents to a value determined by a reference voltage which is temperature compensated. Thus, the biasing op-amp automatically compensates for temperature variations and manufacturing uncertainties in devices throughout the entire interpolator.

Abstract: Rather than increasing the mass of the structure, the structure in a sensor system suspends its substrate from some mechanical ground. Motion of the substrate relative to the mechanical ground thus provides the movement information. To those ends, the sensor system includes a base, a substrate, and a flexible member suspended from at least a portion of the substrate. At least a portion of the flexible member is capable of moving relative to at least a portion of the substrate. In addition, the flexible member is secured to the base, thus causing the substrate to be movable relative to the base. Moreover, the mass of the substrate is greater than the mass of the flexible member. The substrate and flexible member are configured to interact to produce a motion signal identifying movement of the base.

Abstract: An integrated circuit has a substrate with a back side and a front side. The front side has both a working area and a front side contact in electrical communication with the working area. In a similar manner, the back side has first and second back side contacts. A first conductive path extending through the substrate electrically connects the front side contact and the first back side contact. In addition, a second conductive path electrically connects the first back side contact with the second back side contact.

Abstract: A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.

Abstract: A system for processing a sound input to a MEMS microphone in a voice communication device, such as a cellular telephone. The system includes the microphone and a processing microchip. The processing microchip includes a differential receiver that receives the signal output of the microphone on one input and a voltage that biases the microphone on the other input. The output of the differential receiver represents the audio signal from the microphone, while noise signals induced on connections between the microphone and microchip are received equally on the differential receiver inputs, thereby cancelling. Further, the processing microchip also includes a bias voltage generator circuit for supplying a bias voltage to the microphone. Noise that is coupled onto or is inherent in the bias voltage generator circuit or couples onto the signal path from the bias voltage generator to the microphone will traverse substantially symmetrical paths to the differential receiver.

Abstract: A microphone microchip for a voice communication device. The microchip receives and processes an audio signal from a microphone. The microchip incorporates an RF filter that substantially attenuates noise signals at RF frequencies, while passing audio signals, substantially unattenuated. The filter is inserted between ports through which RF carrier signal noise can enter the microchip and internal elements of the microchip that provide a nonlinear response. Thus, modulated RF carrier noise is attenuated before this noise can interact with the nonlinear elements to convert the modulated carrier noise to audible interference. Corruption of microphone signals is thereby avoided.

Abstract: An apparatus for biasing a transistor, comprising: a controllable bias generator; a test circuit; a digital Mth order differentiator responsive to an output of the test circuit; and a controller responsive to the digital Mth order differentiator for controlling the controllable bias generator; wherein the test circuit is configured to calculate an Lth order derivative of the transistor's performance.

Abstract: In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.

Abstract: A memory device has at least one sub array of memory cells having data columns and at least one spare sub array having spare columns. In one embodiment the sub array of memory cells and the sub array having spare columns are the same sub array. Individual elements in the sub arrays of memory cells can be repaired using an individual element from the spare sub array.

Abstract: A mass includes a first set of drive fingers interdigitated with a first array of fixed drive fingers and a second set of drive fingers interdigitated with a second array of fixed drive fingers. Each array of fixed drive fingers is affixed to a substrate using a plurality of anchors. The anchors for the first and second arrays of fixed drive fingers are arranged to be co-linear in a lateral direction relative to the motion of the mass.

Abstract: A ?? modulator system with start up transient suppression includes a ?? analog to digital converter having predetermined internal signal limits; an envelope control circuit for attenuating the input signal to the ?? analog to digital converter and a control circuit responsive to a start/reset signal to enable for a limited time the envelope control circuit to attenuate the input signal to maintain the ?? analog to digital converter internal signal substantially within the predetermined internal signal limits.

Abstract: A calibration system for an inertial sensor includes a calibration module for processing an output value produced by the inertial sensor, the output value related to a detected movement of an object, wherein the calibration module calculates an offset value from a plurality of output values, and memory operatively coupled with the calibration module, the memory capable of storing the plurality of output values and/or the offset value, wherein the inertial sensor is calibrated using the calculated offset value.

Abstract: A sensor has a die (with a working portion), a cap coupled with the die to at least partially cover the working portion, and a conductive pathway extending through the cap to the working portion. The pathway provides an electrical interface to the working portion.

Abstract: Structures and methods are provided for capturing data from a data bit stream. They primarily generate successive bit sample sequences that each comprise N interleaved bit sample phases, identify subsampling strings formed of less than N consecutive bit samples with the same bit sample value, invalidate the bit sample phase of any bit sample that adjoins the strings, and then form data with successive bit sample phases that remain valid after the invalidating step. From more than one valid bit sample phases, they identify a preferred valid bit sample phase as one whose bit samples least often adjoin transitions from one bit sample value to a different bit sample value and then form the data with the preferred valid bit sample phase. Preferably, copies of the bit sample sequences are delayed along a delay path to facilitate the identifying and invalidating steps and subsequently, valid bit sample phases are multiplexed from the delay path.

Abstract: An analog to digital converter comprising a conversion engine having redundancy therein; and a dither device for applying a dither to the conversion engine; and a controller adapted to operate the conversion engine to perform a successive approximation conversion of the analog input, and wherein the dither is removed prior to completion of the analog to digital conversion.

Abstract: A capacitive sensor including a housing having a hermetically sealed cavity, a plate in the cavity, a diaphragm forming a part of the cavity and spaced from the plate, a conductive layer on the first diaphragm, and a second conductive layer on the plate, the first and second conductive layers being the electrodes of a capacitor whose capacitance varies with the position of the diaphragm relative to the plate.

Abstract: The present invention relates to a system and method for digitally compensating signal converters and in particular a digital to analog converter which receives digital input data for a digital to analog converter and supplies anti-function digital coefficients derived from the error function of the digital to analog converter and corresponding to the digital input data and applies the anti-function digital coefficients to the digital input data to pre-condition the digital input data to compensate for the error function of the digital to analog converter. The invention also extends to analog to digital converters.

Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

Abstract: A signal conditioning circuit for a latching comparator comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.

Abstract: A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.