Abstract: A circuit and method for trimming and simulating the effect of trimming a plurality of IC parameters. Trim signals which affect respective IC parameters are generated with respective digital-to-analog converters (DACs) in response to digital bit patterns. A parameter to be trimmed is selected, a bit pattern is applied to a DAC and a trim signal generated, and the value of the parameter that results is measured. Bit patterns are iteratively created until one is identified that brings the parameter within an acceptable range. The identified bit pattern is then permanently encoded using programmable subcircuits containing poly fuses. The bit patterns are received serially to conserve I/O pins. A number of DACs are provided to enable a number of different parameters to be simulated and trimmed. A switching network is provided that selectably switches otherwise inaccessible internal nodes to an I/O pin for measurement. The trimming circuitry.

Abstract: A direct conversion receiver having a homodyning section fed by a received radio frequency signal having a carrier frequency and reference signal having the carrier frequency; and a filter coupled to the monodyning section. The filter includes a plurality of serially coupled high pass filter stages. The high pass filter section acts as a DC offset correction loop that eliminates the serial effect of many amplifier sections on DC offsets arising within components, while maintaining a sufficiently low cutoff frequency to avoid adversely impacting information integrity at higher frequencies. The high pass filter sections also enable the integration of the needed capacitors, thus minimizing external components and connections. Each filter stage includes an amplifier and a low pass filter coupled in a negative feedback arrangement with the amplifier. Each low pass filter is adapted to have the cutoff frequency thereof switch from an initial high cutoff frequency to a subsequent lower cutoff frequency.

Abstract: A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at least one control information register for storing control information used by the bit transfer mechanism.

Abstract: A data bus system with data integrity verification is arranged so that a bus device receiving a message always responds by sending a check sequence back to the message originating device; i.e., a check sequence is automatically returned to a message originating device as part of every bus transaction. The originating device reads the returned check sequence and uses it to verify the integrity of the data transferred between the two devices. The check sequence can be created by the receiving device based on the data conveyed, or the receiving device can simply echo back a check sequence that is appended to the incoming data.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: A method and circuit for providing a reference voltage to a charge balance circuit. The method includes transferring charge corresponding to VBE and charge corresponding to &Dgr;VBE to a summing node of the charge balance circuit, where VBE is a voltage produced across a p-n junction and where &Dgr;VBE is a difference between two VBE voltages. With such method, instead of forming a bandgap reference circuit which produces a bandgap reference voltage and applying such voltage to the reference sampling and charge transfer circuit, charge corresponding to VBE and charge corresponding to &Dgr;VBE are transferred to the input summing node of the modulator in correct proportion and with a polarity corresponding to the modulator output.

Abstract: Feedback control systems and methods are provided for correcting residue signal offset errors in subranging ADCs. The systems and methods eliminate clock-to-clock offset changes and reduce noise generation. An exemplary control system includes a feedback loop around a residue sampler and a residue amplifier that includes a) a feedback sampler that resamples the output signal of the residue sampler to produce a resampled residue signal, and b) an offset current generator that delivers an offset current to the residue amplifier with a current magnitude that is responsive to the resampled residue signal. The sampling of the residue and feedback samplers is time shifted to block the propagation of spurious signals that are typically generated in DACs of the subranging structure.

Abstract: A die has a part that is sealed with a cap. The seal can be hermetic or non-hermetic. If hermetic, a layer of glass or metal is formed in the surface of the die, and the cap has a layer of glass or metal at a peripheral area so that, when heated, the layers form a hermetic seal. A non-hermetic seal can be formed by bonding a cap with a patterned adhesive. The cap, which can be silicon or can be a metal paddle, is electrically coupled to a fixed voltage to shield the part of the die.

Abstract: A shaped pulse generation circuit for applications such as automatic test equipment pin drivers employs an active feedback circuit that adds a pre-emphasis to the output pulses, thereby compensating for the effect of the transmission system between the pin driver and the device under test. Current pulses are applied to the pin driver output transistors in conjunction with the production of rising and falling output pulse edges to produce edge overshoots that are mitigated during pulse transit to the device under test. The driver circuit together with the pre-emphasis active feedback circuit can be integrated onto a single chip, with an additional programming circuit employed to control the amount of pre-emphasis.

Abstract: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.

Abstract: A first device receives and processes signals from a communication link that supports a plurality of signal protocols. The device comprises a converter, coupled to the communication link, that outputs a sampled data stream, and a digital filter that filters the sampled data stream to separate signals associated with different signal protocols. A second device receives a first input sampled data stream representative of a first signal to be transmitted and associated with a first signal protocol and a second input sampled data stream representative of a second signal to be transmitted and associated with a second signal protocol, and combines the data streams into an output data stream which may be coupled to the communication link.

Abstract: A non-inverting feedback amplifier with high disabled impedance includes a disableable signal amplifier; a feedback network having an input node, a feedback node and a reference node; the signal amplifier having a first input for receiving an input signal and a second input for receiving a feedback signal from the feedback node; and a reference buffer including a reference amplifier with its output directly connected to the reference node without additional series switching elements, a first input connected to a reference voltage, and a second input connected to its own output for mirroring at its output the reference voltage at its first input when the reference buffer and signal amplifier are enabled and presenting a high impedance between the feedback network and the reference voltage when the signal amplifier and reference buffer are disabled.

Abstract: Latch systems and methods are configured to temporarily latch trim signals in experimental combinations of set and reset states and, subsequently, to permanently latch the trim signals in a preferred combination (i.e., a combination that optimizes the performance parameters of an electronic circuit). Latch systems of the invention include a latch, a reset driver, a temporary-set driver and a permanent-set driver and are particularly suited for determining a preferred combination of set and reset states prior to permanently latching this preferred combination.

Abstract: Apparatus, and method, for producing a signal representative of a non-linear function of an input signal. The apparatus includes a feedback loop having a sigma-delta modulator fed by the input signal and a feedback signal, such feedback signal being a non-linear function of the output of the modulator. The output of the sigma-delta modulator is a stream of m-bit digital words. The output of the sigma-delta modulator is fed to an filter for converting the stream of m-bit digital words produced by the sigma-delta modulator into a corresponding stream of n-bit digital words. The n-bit and m-bit streams of digital words are fed to a multiplier. The multiplier produces an series of digital words, each one of the digital words representing the product of one of the n-bit digital words and a one of the n-bit digital words. The series of digital words produced by the multiplier is fed to the sigma-delta modulator as the feedback signal.

Abstract: Differential-signal gate structures are provided in which first and second current-switching modules are coupled to first and second electrical loads with the differential input ports of the modules cross coupled. Although each of the modules separately exhibits an increased propagation-delay response to one input signal sequence, they are never simultaneously exposed to this sequence because of the cross coupling of the input ports. Accordingly, these gate structures have significantly reduced propagation-delay variations.

Abstract: N-bit precision digital-to-analog converters are provided that facilitate realization of precision linearities (i.e., linearities that substantially exceed N-bit linearity). They include a binary-weighted current source, current switches and bidirectional-trim digital-to-analog converters. The binary-weighted current source generates binary-weighted currents that are each coupled to the output port by a respective one of the current switches in response to a respective bit of the digital input signal. The bidirectional-trim digital-to-analog converters generate respective bidirectional trim currents with respective amplitudes and directions. Each of the bidirectional-trim digital-to-analog converters is coupled to provide its bidirectional trim current to a respective one of the current switches for a linearizing adjustment of that switch's binary-weighted current. Preferably, the bidirectional-trim currents are slaved to the binary-weighted currents.

Abstract: A CMOS amplifier includes a FET differential input stage, with the input transistors' sources connected to a common tail current. A first current mirror reflects the drain current from one input FET to the other at a first node. A pair of FETs are connected to conduct respective currents in response to the voltage at the first node. One of the currents drives a load at a second node, which is connected to one of the input stage gates such that the output voltage tracks an input voltage applied to the other input stage gate. The other current is reflected via a second current mirror to provide the common tail current. By properly sizing the FETs to achieve particular current densities, the tail current is automatically varied to adjust the operating point of the differential input stage such that, when the amplifier is in equilibrium, the drain voltages of the input FETs are kept equal over a wide range of output currents.

Abstract: Methods are provided for separating microcircuit dies from a wafer, which includes microcircuit dies containing componentry on a circuit side thereof and streets separating the dies from each other. A first wafer mount film is affixed to the circuit side of the wafer, and the dies are detached along the streets with the circuit side of the wafer fixed to the first wafer mount film, thereby forming a divided wafer. A second wafer mount film is fixed to the back side of the divided wafer, and the first wafer mount film is removed from the divided wafer so that the dies remain fixed to the second wafer mount film with their circuit sides exposed. The second wafer mount film preferably has greater adhesion to the divided wafer than the first wafer mount film when the first wafer mount film is removed from the divided wafer. The first wafer mount film may comprise a protective film having holes aligned with fragile components on the dies and a cover film that covers the holes.

Abstract: An electronic programmable read-only-memory (EPROM) is provided having a field effect transistor with the gate electrode thereof coupled to a capacitor adapted to store charge produced in a channel region of the transistor in response to a logic state programming voltage applied between one of the source and drain regions and the gate electrode. The field effect transistor and the capacitor are formed in a common semiconductor body along with CMOS transistors. The field effect transistor has relatively heavy doped source and drain regions separated by an oppositely doped channel region. A gate electrode is disposed over the channel region. Lightly doped regions, having the same conductivity type as the source and drain regions, extend laterally from the source and drain regions to peripheral regions of the channel region to suppress generation of “hot” electrons in the transistor and the CMOS transistors.

Abstract: An electronic filter has an input connector adapted for electrical connection to a complimentary output connector of an asymmetrical digital subscriber line. The input connector has an input voltage node for providing electrical input signals to the electronic filter. Similarly, the filter has an output connector adapted for electrical connection to a complimentary input connector of a data receiving device. The output connector has an output voltage node for providing electrical output signals from the electronic filter. The filter selectively passes frequency components of the electrical signals, frequency components below a predetermined corner frequency passing from the input connector to the output connector, frequency components above the predetermined corner frequency not passing from the input connector to the output connector.