Abstract: Display interface embodiments are provided to capture various types of analog video signals and digitize them for presentation on advanced digital displays (e.g., computer displays and television displays). The embodiments include at least an error converter channel and a reference converter channel that can each amplify an analog input signal S with a fixed gain G and a programmed gain g and convert the amplified signal to a corresponding digital code. The embodiments also include a channel controller that is configured to conduct process steps that adjust the transfer function of the error converter channel to conform to (e.g., matches) the transfer function of the reference converter channel.

Abstract: A system and method transmits data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data is converted to frequency independent data. A ratio of a number of data clock cycles to a number of reference clock cycles is determined and transmitted. The frequency independent data and header data are transmitted, at a fixed rate, to a receiver, the fixed rate being a frequency greater than the frequency of the associated data clock signal. The received the frequency independent data is converted to frequency dependent data based upon the received determined ratio. The communication channel may include an optical fiber and a tension member wherein control data is transmitted along the tension member and graphic data is transmitted along the optical fiber.

Abstract: A memory having multiple locations for data storage is updated by performing the following method. The memory locations are grouped into commonly accessible groups of one or more data locations. First, a control array is provided. The control array is associated with a predetermined type of memory update operation, and has a local indicator for each commonly accessible group of memory locations respectively. Next, the instruction stream to the memory is monitored to determine the current memory operation type, and the set of groups of memory locations upon which the current operation is to be performed. If the current memory operation is an operation of the predetermined type, the control array is updated. If the current operation is an operation other than the predetermined type, the state of the respective local indicator of each group of the set is determined. The current operation is then performed upon each group in the set in accordance with the state of its respective local indicator.

Abstract: Variable attenuation systems having continuous input steering may be used to implement vector or quadrature modulators and vector multipliers. Discrete implementations of attenuators with continuous input steering may have two outputs which may be cross-connected to provide four-quadrant operation. A symmetrically driven center tap may provide improved zero-point accuracy.

Abstract: A Successive Approximation Routine converter is provided in which a comparator is responsive to an output of a first Digital to Analog Converter, and an output of a second Digital to Analog Converter and to a DAC common mode output reference voltage, and wherein the comparator provides data to a SAR controller indicating which one of the DAC outputs is greater than the other, and how a common mode voltage on the DAC outputs compares to the reference voltage. On this basis the SAR controller can add or subtract a common mode offset to the trial words being presented at a given bit trial such that both differential and common mode convergence is achieved.

Abstract: Reference generator embodiments are provided with low output impedances to enhance reference stability in the presence of varying loads. The generators are structured to provide these impedances in an efficient manner (i.e., with low supply currents) and also to provide both sink and source currents to better handle large transient current demands. The generators also include cascode structures that facilitate operation with low values of a supply voltage and that provide a low sensitivity to variations in this supply voltage. The embodiments are especially suited for use in signal converter systems.

Abstract: Analog-to-digital converters (ADCs) generally make code errors as they convert analog display signals to digital display signals of digital displays. Code-correction structures are provided that correct these code errors by initially configuring the ADCs to provide digital signals with redundant resolution. In particular, analog display signal having 2N discrete analog levels are converted with M-bit ADCs wherein M exceeds N. This redundancy is utilized with a controller that distinguishes differences between an occurrence pattern of digital codes and a desired error-free pattern of digital codes. Subsequently, the controller corrects the digital code to reduce the observed differences.

Abstract: A variable attenuation system includes a steering core that continuously steers a signal to an attenuator having multiple inputs. An embodiment having an attenuator constructed from discrete components continuously interpolates a signal between the individual inputs of the attenuator. Continuous interpolation between discrete inputs can also be used with attenuators having continuous structures. A fully integrated embodiment achieves continuous input steering by moving a carrier domain along a continuous attenuator. A separate output stage utilizes adaptive biasing to reduce unnecessary current consumption.

Abstract: Embodiments of the present invention employ differential acceleration computations for detecting free fall conditions. The differential acceleration computations can be based on two-axis or three-axis acceleration measurements, and therefore can be implemented using a two-axis accelerometer or a three-axis accelerometer (or combinations of accelerometers that enable acceleration measurements in two or three axes). When a free fall condition is detected, an appropriate signal can be generated, for example, to place a HDD in a protected state before damage is likely to occur. Differential acceleration measurements can also be used to detect a “safe” condition following a free fall condition.

Abstract: A serial protocol and interface for data transmission from a data transmitter 12 to a data receiver 14 where the propagation delay may be up to several clock cycles long and may be varying slowly. The data receiver provides a clock to the data transmitter. A synchronization signal provided by either the receiver or the transmitter initiates a frame of data transmission at a transfer rate controlled by the clock. The synchronization signal coordinates the transmission of a data header followed by a predetermined number of data bits, known as the frame length. The data receiver uses the header bits to determine the times to sample the subsequent data bits. The length of the frame is limited to provide sufficient likelihood the propagation delay line characteristics have not changed enough to cause a bit error. The system resynchronizes at the beginning of each frame.

Abstract: The present invention relates to an H-bridge controller and method for controlling a common-mode voltage and/or current of an H-bridge circuit. The H-bridge controller comprises a section for receiving a signal indicating at least one of a common-mode voltage and common-mode current of the H-bridge circuit, and a section for generating control signals which determine switching of the H-bridge circuit so as to control at least one of the common-mode voltage and common-mode current of the H-bridge circuit.

Abstract: A bias circuit is disclosed for use in a temperature compensation system. The bias circuit provides a current that is proportional to a temperature variation raised to an nth power where |n|>1 in accordance with an embodiment. In further embodiments, the bias circuit includes a PTAT current source for providing to a driver-stage amplifier a current that is substantially proportional to absolute temperature, and a CTAT current source for providing a current that is complementary to absolute temperature, wherein the PTAT and CTAT current sources coact to provide a PTAT2 reference current that is proportional to an absolute temperature variation to the nth power wherein |n|>1.

Abstract: The invention provides a temperature reference circuit that is adapted to provide a ?Vbe of sufficiently large value that no amplification is required, and therefore any offset contribution is not gained. Using a stacked arrangement of three pairs of transistors, the invention reduces the requirement for multiple resistors within a circuit and can therefore minimize errors due to resistor matching and value. By driving at least some of the transistors with a proportional to absolute temperature (PTAT) current it is possible to ensure that the ?Vbe as a temperature sensitive variable.

Abstract: An overload current limiting circuit includes an output control circuit responsive to a logic input signal for generating a control signal for driving an output device to produce at an output terminal a signal representative of the logic input signal; and a sense circuit for sensing voltage at the output terminal indicative of a current overload and diverting a portion of that current to change the control signal to the output device to limit the overload current.

Abstract: In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine loads each of the plurality of instructions one at time and determines the validity of each instruction. If the instruction is valid, the state machine transfers the instruction to the decoder. If the instruction is invalid or if a no-operation instruction is present, the state machine discards the instruction and immediately loads the next instruction.

Abstract: A single chip digital frequency synthesiser (1) for synthesising a frequency swept synthesised output signal of a selectable frequency sweep comprises a direct digital synthesiser (5) which produces the frequency swept synthesised output signal on an output terminal (7) in response to values of a frequency control digital word applied to a frequency control input (8) thereof by an on-chip data processing circuit (25). An on-chip programmable data storing circuit (12) is programmable to store data indicative of a selected mode in which the digital frequency synthesiser (1) is to operate, and to store data indicative of selectable frequency and the time domains of the frequency swept synthesised output signal to be produced.

Abstract: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.

Abstract: In an inertial sensor, a mass is supported by a number of mass support structures positioned within an inner periphery of the mass. The mass support structures are affixed to a substrate by at least one anchor positioned proximate to the mass' center of mass. A number of sensing fingers are affixed to the mass support structures.

Abstract: The method provides a semiconductor structure and method for forming such a structure that provides for protection for resistive layers formed within the structure from contamination from adjacent layers. By encapsulating the resistive layer in a material that is resistant to the diffusion of contaminants it is possible to protect the resistive material during the processing required to manufacture the structure.

Abstract: A power supply monitoring circuit is provided that utilises an adaptive internal control of the refresh rates of capacitors to reduce the power requirements of the circuit. The circuit provides at an output a signal indicative of the level of the supply voltage relative to a predetermined reference voltage.