Abstract: An analog-to-digital converter including a quantizer and a residue generator, both of which sample an input voltage in parallel. The sampling characteristics of each of the residue generator and the quantizer are designed to substantially match one another. This converter may be used as a low-power ADC front-end circuit that does not require a dedicated sampleand-hold circuit. The front-end circuit consists of two substantially-matched sampling networks, one for the residue generator and the other for the quantizer, inside the first stage of the converter.

Abstract: A resistive DAC (1) comprises a digital input port (2) and an analog output port (3) on which analog resistance output values are outputted in response to corresponding digital input codes on the input port (2). A decoding and control circuit (4) selects appropriate resistors (R1) to (RN) from a resistor chain (5) for providing the analog resistance output of the analog output port (3). A register (7) stores a transfer coefficient in binary code which can be read through the input port (2) and by which each digital input code should be multiplied in order to produce an analog resistance output of predetermined value. The transfer coefficient in the register (7) takes account of variations in internal circuit parameters which causes the analog resistance outputs on the output port (3) to be less than they would in an ideal resistive DAC.

Abstract: A multiprocessor system includes a distributed bus arbitration system in which bus arbitration takes place simultaneously on each of the multiple processors connected to the bus. Each processor has a local arbitrator of common configuration with the other local arbitrators and a dedicated request line. Each local arbitrator is connected to each dedicated request line to monitor signals on lines indicative of requests for mastership of the bus by the processors. Since each local arbitrator is of common configuration with the other local arbitrators, is operating synchronously with the other arbitrators, and is provided with a similar set of inputs, each arbitrator will arrive at the same conclusion as to which processor is to become bus master. Accordingly, an external bus arbitrator is not required and acknowledge lines are not required to communicate signals indicative of the result of the bus arbitration to the processors.

Abstract: High-speed sampler methods and structures are provided to enhance the correlation between an input signal Sin and a corresponding sampler output voltage Vout. An input buffer is enabled during sampling time periods and disabled during holding time periods. In the sampling time periods, a sampling capacitor Cs is directly charged through the input buffer and the capacitor's bottom plate to a charge that corresponds to the input signal Sin. In the holding time periods, the disabled input buffer is isolated from the sampling capacitor Cs and a common-mode signal Scm is directly coupled to the capacitor's bottom plate to provide the output voltage Vout at the capacitor's top plate. Preferably, an output capacitor Co is coupled to the sampling capacitor Cs and charge from the sampling capacitor Cs is transferred to the output capacitor Co.

Abstract: A data processor is provided which has integrated therein at least two of a bootstrap memory, a program memory and a data memory, wherein the at least two memories are of the same construction. In an exemplary embodiment, the memories are flash EEPROM memories. The data memory is provided with registers for temporarily storing the contents of an entire row of memory such that modifications can be easily made to a single bit within the row by storing the contents of the row, erasing the row, modifying the data and storing the data back in the row.

Abstract: A dynamic bridge system with common mode range extension includes a dynamic bridge circuit having a pair of input terminals for receiving common mode and normal signals, a pair of intermediate terminals and an output terminal and reference terminal; a differential amplifier has its inputs connected to the intermediate terminals and its output connected to the output terminal; a pair of balanced loads is each connected at one end to an intermediate terminal; and an inverting amplifier responsive to the common mode signal at the inputs of the differential amplifier drives the other ends of the balanced loads in opposition to changes in the common mode signals at the inputs of the differential amplifier.

Abstract: First and second clocked digital sources are provided in each of two data paths, and are clocked by respective direct and complementary clock pulses. The clocked outputs of these devices are directed to a multiplexer where the inter-leaved data path signals are recombined into a single output line. This multiplexer includes clocked transmission gates, the clock signals for which are shifted in time by 90° from the clock signals applied to the originating signal sources. The result is that additional time is made available for sampling the digital signals applied to the multiplexer.

Abstract: A high permeability magnetic core structure introduces a magnetic field to an intergrated circuit during testing. The magnetic core is mounted in an automatic tester and is integrated into the mechanical test site assembly that holds the integrated circuit in place during testing. Wound wire coils, mounted on the core structure, generate the magnetic field that is used for the test.

Abstract: An operational amplifier having two differential input stages. A first one of the stages comprises a pair of first input transistors and another one of such stages comprises a pair of second input transistors. The second input transistors are complementary in type to the first input transistors. A comparator is fed by a sense signal and a reference signal, such sense signal being related to at least one of a non-inverting and an inverting input signal fed to the operational amplifier. The comparator produces a control signal in accordance with a difference between the sense signal and the reference signal. A switching network is responsive to the control signal and couples an output of either the first one of the stages or the second one of the stages to an output of the operational amplifier selectively in accordance with the control signal.

Abstract: A switching voltage regulator employs a “dual modulation” scheme to control the regulator's switching components. A control circuit indirectly monitors load current. When the load decreases, the control circuit reduces both the duty ratio and the frequency of the control signals which operate the switching transistors, thereby maintaining a high efficiency level over a wider output current range than can be achieved with fixed-frequency control signals. In a preferred embodiment, the regulator employs three operating modes. For heavy loads, the switching components are operated at a constant frequency. For moderate-to-light loads, the dual modulation control scheme is used. For light loads, the regulator enters a “pulse-skipping” mode which can achieve very low operating frequencies to further improve efficiency.

Abstract: An IC resistor and capacitor fabrication method comprises depositing a dielectric layer over existing active devices and metal interconnections on an IC substrate. In a preferred embodiment, a layer of thin film material suitable for the formation of thin film resistors is deposited next, followed by a metal layer that will form the bottom plates of metal-dielectric-metal capacitors. Next, the capacitors' dielectric layer is deposited to a desired thickness to target a particular capacitance value, followed by the deposition of another metal layer that will form the capacitors' top plates. The metal layers, the capacitor dielectric layer, and the thin film material layer are patterned and etched to form TFRs and metal-dielectric-metal capacitors as desired on the IC substrate. The method may be practiced using any of several alternative process sequences. For example, the bodies of the TFRs can be formed before the deposition of the capacitors' layers.

Abstract: A buffer circuit includes a delay circuit which is interposed between a signal source and a following circuit. The delay circuit propagates a signal from an input to an output; the signal has associated desired timing relationships between its rising and falling edges. The delay circuit controls the propagation delays of the signal's rising and falling edges such that when the signal arrives at a selected downstream node, it has the desired timing relationships. The delay circuit adjusts the propagation delays in accordance with two correction signals: one which reduces errors induced by imperfections in the signal path through which the test signal propagates, and one to reduce errors due to thermal effects that arise when propagating a periodic test signal having a duty cycle other than 50% through the signal path.

Abstract: A method for stabilizing thin film structures fabricated on an I.C. wafer requires the performance of a rapid thermal annealing (RTA) step after the thin film material, preferably silicon-chromium (SiCr) or silicon chromium carbide (SiCrC), is sputtered onto the wafer. The RTA step stabilizes the TF and thereby increases the film's integrity. With the TF structures stabilized, the effect of subsequent high temperature process steps on the film is reduced. The stabilization method enables TF resistors thereby formed to attain a higher degree of accuracy, and thus to improve the ability with which resistors can be matched. Resistor TCR and sheet rho consistency are also improved, both within a given wafer and from wafer to wafer.

Abstract: A micromachined accelerometer is hermetically sealed in a reduced oxygen environment to allow organics to survive high temperature sealing processes.

Abstract: A method for capping active areas of a semiconductor wafer uses photolithography to define areas of sealant on the cap wafer to thereby reduce the amount of space required for attaching the cap wafer to the semiconductor wafer carrying active areas to be capped. Using photolithography in this manner increases the amount of space on the semiconductor wafer that can be used to form active areas which, in turn, improves the density of active area on the semiconductor wafer. In one embodiment, the method includes the steps of applying a photoimageable layer, photoimaging the photoimageable layer to define a pattern including remaining regions of the photoimageable layer and removed regions of the photoimageable layer, and using the pattern to define the sealant regions on the semiconductor wafer.

Abstract: An improved successive approximation analogue-to-digital converter system including a D/A converter and a comparison capability, wherein a first trial value is stored in a successive approximation register and a comparison is made of relative amplitude of D/A converter output with respect to analogue signal amplitude, and an iterative process is performed in which a subsequent trial value is stored in the successive approximation register before the comparison is repeated. The improvement comprises conducting only one comparison for each trial, with the subsequent trial value for a plurality of iterations being greater than one-half the first trial value, such that a first trial value determined in error is corrected during subsequent iterations. Apparatus implementing the improved successive approximation A/D is also described.

Abstract: A dual-edge pulse-triggered flip-flop comprising a gated data latch and a gated scan latch coupled in series with the data latch. In normal operation, the data latch captures a data input D in response to clock pulses ckp generated on each edge of a system clock ck. During an input scan operation, a selected stimulation bit presented on a scan input SI is transferred first into the scan latch in response to a scan input clock ak, and then into the data latch in response to a scan output clock bk. This stimulation bit is simultaneously presented on a scan output SO. During an output scan operation, a data bit Q presented on the scan input SI is transferred first into the scan latch in response to the scan input clock ak, and then into the data latch in response to the scan output clock bk. This data bit is simultaneously presented on the scan output SO.

Abstract: A high-frequency RMS-DC converter having extended dynamic range operates by dynamically at low cost by adjusting the scaling factor (denominator) of a detector cell such as a squaring cell. The output from the squaring cell is averaged to generate a final output signal which can be fed back to a scaling input for operation in a measurement mode, or used to drive a power amplifier in a controller mode. By implementing the squaring cell as a transconductance cell using a modified multi-tanh structure, the scaling factor can be adjusted by dynamically changing the tail current through the cell which, in the measurement mode, is achieved by connecting the averaged output back to the squaring cell. An exponentially responding amplifier can be used in the feedback loop to provide a linear-in-dB output characteristic.

Abstract: A direct-digital synthesizer for generating a waveform includes a digital accumulator fed by a phase increment word and a series of clock pulses for successively adding the phase increment word to produce a series of N bit phase words. A table or trigonometric engine produces sine and cosine digital signals related to the M most significant bits of the phase word produced by the accumulator. A feedback loop is fed by truncation error words comprising at least a portion of N-M least significant bits of the N bit phase words producing truncation error compensation words. The feedback loop includes a digital filter. The feedback loop includes a digital filter. The feedback loop including the digital filter provides a low pass truncation error response to the truncation error having at least one zero in the transfer function thereof at DC.

Abstract: A differential switch accepts a binary control signal and its complement (which may be skewed with respect to the control signal) and latches both signals simultaneously. The latched output signals drive the control terminals of a differential switch pair which connects one of two terminals to a third terminal, depending upon the state of the control terminals. The differential switch may optionally include an inverter which complements the binary control signal, thus eliminating the need for external inversion of the control signal. The switch is particularly applicable for use in a digital to analog converter.