Abstract: A bandgap reference circuit provides an output reference voltage that is generally insensitive to fluctuations in supply voltage, ambient temperature, and output load current. A current regulator establishes an output whose variations are reduced, preferably logarithmically, relative to variations in a supply voltage. A bandgap generator fed by the output current provides an output reference voltage with similarly suppressed variations. A control amplifier biases the bandgap generator to provide a high level common-mode rejection of various error sources.

Abstract: A power-on reset circuit employs all-CMOS circuitry to initiate a reset signal when the circuit's power supply voltage is low, and terminate the signal in response to the supply voltage exceeding a reference voltage by at least the greater of the threshold voltages of PFET and NFET transistors employed in the circuit. A diode-connected bipolar transistor is implemented with an FET-compatible circuit structure to establish the reference voltage, which compensates for the possibility of fabrication tolerances.

Abstract: An isolator having a driver circuit which responsive to an input signal drives appropriate signals into one or more coils which are magnetically coupled to one or more corresponding MR or GMR elements whose resistance is variable in response to the magnetic field applied by the coil(s), and an output circuit that converts the resistance changes to an output signal corresponding to the input signal. A Faraday shield is interposed between the coil(s) and the MR or GMR elements. Common mode transients applied to the driver are capacitively coupled from the coil(s) into the Faraday shield and therethrough to ground, instead of into the MR elements. A second Faraday shield may be disposed in spaced relationship with the first Faraday shield and referenced to the potential of the MR elements for even greater common mode rejection. The entire structure may be formed monolithically as an integrated circuit on a single substrate, for low cost, small size, and low power consumption.

Abstract: A data processor is provided with an embedded debugger. The debugging function is provided by the execution of a debugging program which is stored in reserved, non-volatile memory which is internal to the data processor. During the debug mode, the data processor allows the internal registers used during execution of a user program to be examined. Debug operation can be initiated via debug instruction which replaces an existing instruction in the user code, the replaced instruction being held in a special purpose register such that it can be executed on return from the debug mode. Single step operation of the data processor can be performed in debug mode and data and instructions can be exchanged with the data processor in debug mode, optionally via a single pin so as not to sacrifice any user resources.

Abstract: A micromachined device is provided that establishes select dimensional relationships between micromachined structures to achieve correlation in dimensional variation among these structures.

Abstract: An integrated circuit chip having formed thereon a voltage control circuit supply adapted to provide one of a pair of voltages selectively in accordance with an operating mode of the circuit. The circuit includes a comparator circuit fed by the pair of voltage sources. A first switch is controlled by the comparator circuit. A first one of the pair of voltage sources is fed through a second switch which may be a transistor or a diode. An input of the first switch is fed to a second one of the pair of voltage sources.

Abstract: A system having an adjustable gain includes: a modulator, for producing a stream of digital words representative of an input analog signal; and, a gain adjustor, fed by a gain signal representative of the adjustable gain, for converting the stream of digital words produced by modulator into an output stream of bits representative of the gain adjusted input analog signal. The stream of stream of digital words produced by modulator, which represent the gain adjusted input analog signal, can be produced with an register for storing the gain signal and an adder. Further, the stream of digital words bits produced by modulator can fed to an compact sinc filter for conversion into digital words which represent digital samples on the gain adjusted input analog signal. The system includes a sigma-delta modulator for producing a stream of digital words having values, M or N, such stream of digital words bits being representative of an input analog signal, X(t) fed to the modulator.

Abstract: A method of shielding light from rows and columns of an array of pixels of a CMOS image sensor includes the steps of: providing a first layer of metal shielding above the rows and columns of the array; and providing a second layer of metal shielding above the first layer. The method further includes forming slots within each of the first and second layers of metal shielding, such that the slots of the first layer are misaligned with the slots of the second layer. A light shield for shielding columns and rows of an array of pixels in a CMOS image sensor includes a first metal layer located above the columns and rows of the array, and a second metal layer located above the first metal layer. Each of the first and second metal layers includes slots. The slots are formed such that the slots of the first layer are misaligned with the slots of the second layer.

Abstract: A semiconductor magnetic field sensor including a substrate; a semiconductor moveable element suspended above the substrate, the moveable element being configured to have a current passed therethrough and to deflect perpendicularly with respect to an applied magnetic field; and at least one fixed semiconductor element arranged adjacent to the moveable element, the moveable element being deflected to or away from the fixed element in response to an applied magnetic field.

Abstract: A synchronization pulse detector for detecting a synchronization pulse within an input signal. The input signal has “level” portions (i.e., substantially non-time varying portions) and “transition” portions (i.e., substantially time varying portions). The pulse detector includes a pulse shape detector for determining each time the input signal has a sequence of a first “level” portion, followed by a first “transition” portion, followed by a second “level” portion, followed by a second “transition” portion followed by a third “level” portion, one of the first and second “transition” portions being positive and the other one of the first and second “transition” portions being negative. Each time such sequence is determined a pulse_shape detected pulse is produced. An evaluator is provided to reject invalid pulse_shape detected pulses.

Abstract: A digital-to-analog converter (DAC) including an array of switched input capacitors which store samples of charge proportional to a digital input signal, and an analog output circuit which integrates the samples of charge to generate an output analog signal that is proportional to said digital input signal. The capacitors store a binary representation of the digital input signal. The output circuit includes a zeroth order sample-and-hold circuit having first and second stages with respective first and second operational amplifiers. The first and second stages are cascaded together during a sample phase so that the analog output signal is stored in a capacitor in a feedback path between the output of the second stage and the input of the first stage, and are disconnected from one another during a hold phase so that the first stage is auto-zeroed and the second stage holds the analog output signal as a continuous time output.

Abstract: D flip-flop structures are provided which respond to a DATA signal and a clock (CLK) signal by generating an output signal whose state during each clock pulse is that of the DATA signal at that pulse's leading edge and whose state between clock pulses is reset to a selected logic value. Accordingly, these flip-flops can function (e.g., monitor events in the DATA signal or generate sequences of trigger pulses) at the clock rate.

Abstract: A precision op amp test circuit employs latching relays, the contacts of which are latched open or closed as necessary to make test measurements. The relays' metal contacts ensure low resistance conductive paths, and because the coil of a latching relay need be energized only briefly to latch the contacts, the heating duty cycle of the coils can be kept low to substantially eliminate the accuracy-degrading thermal E.M.F. generated by the heat from the energized coil of a conventional relay. The test circuit is advantageously used for testing both VOS and IB for high precision, low-VOS op amps.

Abstract: An analog to digital conversion system having a plurality of analog to digital converters (ADCs). Each one of such ADCs is configured to convert a corresponding one of a plurality of analog signals into a corresponding sequence of digital words. The ADCs have different degrees of conversion performance. A source of the pulses is included. Each one of the ADCs is configured to provide a corresponding one of the sequences of digital words in response to the pulses. Each one of the digital words in each of the sequences is provided at substantially the same time. A controller is provided for interrupting and/or changing the configuration of one or more of the ADCs. The controller provides the interrupt and/or change in configuration with a priority to one of the ADCs over the other one of the ADCs.

Abstract: A sample and hold circuit having a semiconductor with a field effect transistor therein. The field effect transistor has a channel in the semiconductor, a source region in the semiconductor, a drain region in the semiconductor a front-gate disposed over the channel, and a back-gate in the semiconductor under the channel. The front-gate and back-gate are configured to control a flow of carriers in the semiconductor through a length of the channel between the source region and the drain region. A capacitor is connected to one of the drain and source regions. The other one of the source and drain region is configured for coupling to an input signal. A switch is responsive to a sampling signal to electrically connect a constant electrical potential between one of the source and drain regions and back-gate during a tracking phase. In one embodiment, the sample and hold circuit includes a second switch to electrically a second constant potential between the front-gate and one of the source and drain.

Abstract: A high speed, multiple input restrictive OR circuit with fully differential inputs and output is used in applications in which only one input can be active at a time. N differential voltage inputs are converted into N corresponding differential current signals of unit current values. The current signals corresponding to active complement input signals are summed together, with a compensation current equal to (N−1) current units subtracted from the total. The resulting compensated complement currents together with any active input current form a single differential current that indicates the logic state at the input. This differential current is preferably converted to a buffered output differential voltage in an output stage. For high accuracy applications, a common unit reference current is used to generate both a scaled compensation current and unit input stage source currents.

Abstract: A rail-to-rail op amp output stage is configured to provide one or more additional base drive paths for each of its output transistors, reducing the stage's distortion and increasing its maximum output current without substantially increasing quiescent current. The additional base drive paths reduce the demand on the transistors driving the output transistors, lowering the distortion they might otherwise contribute to the output current. In a preferred embodiment, the collectors of the stage's clamp transistors are connected to the bases of their opposing output transistors, so that each clamp transistor provides an additional base drive path to a respective output transistor, thereby increasing maximum output current without substantially increasing quiescent current, and substantially reducing crossover distortion.

Abstract: A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic signal from the isolation barrier and for providing an output signal that indicates the transitions in the logical input signal.

Abstract: A system for a providing addresses to each one of a plurality of addressable integrated circuits. The system includes a plurality of address select circuits, each one thereof being coupled to a corresponding one of a corresponding plurality of addressable integrated circuit. Each one of such integrated circuits has an address select pin adapted to receive a signal from the corresponding one of the address select circuits. The signal is indicative of an address for such one of the plurality of addressable integrated circuits. Each one of such address circuit includes a signal source connected to the pin and a circuit for coding such signal source into a selected one of more than three predetermined signal levels.

Abstract: An N-bit DAC converts an N-bit digital word to an analog voltage. An n-bit modified string DAC, including no more than 2n taps, receives as an input, n MSBs of the N-bit digital word and provides the analog voltage as an output. An m-bit interpolating DAC, coupled to the n-bit modified string DAC, receives as an input, m LSBs of the N-bit digital word, and provides an analog output to the string DAC. Preferably, n=m=N/2. In an embodiment, the interpolating DAC includes first and second current DACs, each of which provides current to or from the n-bit modified string DAC, depending on the level of the LSBs.