Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.

Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.

Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.

Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.

Abstract: A method of producing a MEMS device provides a MEMS apparatus having released structure. The MEMS apparatus is formed at least in part from an SOI wafer having a first layer, a second layer spaced from the first layer, and an insulator layer between the first layer and second layer. The first layer has a top surface, while the second layer has a bottom surface facing the top surface. After providing the MEMS apparatus, the method increases the roughness of at least the top surface of the first layer or the bottom surface of the second layer.

Abstract: A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data.

Abstract: A radio frequency output power control system for use in communication systems is disclosed. The power control system is used for a modulation scheme having a non-constant amplitude envelope and comprises a power amplifier having a power amplifier input for receiving an input signal with a non-constant amplitude envelope, a power control input for receiving a power control input, and a power amplifier output for providing an amplified output signal. The power control system also includes a track and hold circuit for tracking a measured reference power signal that is representative of a modulation of the input signal, and subtraction means for subtracting an output of the track and hold circuit from the measured reference power signal to provide a difference signal that is coupled to the power control input.

Abstract: A digital frequency measurement system including first and second digital differentiators responsive to first and second digital quadrature signals representative of first and second quadrature modulated input signals that represent binary data having a center frequency equal to a predetermined IF frequency for generating first and second differentiated signals, first and second processing circuits responsive to the first and second digital quadrature signals representative of the modulated input signals and the first and second differentiated signals for multiplying the first differentiated signal by the second quadrature digital representation of the input signals and multiplying the second differentiated signal by the first quadrature digital representation of the input signals to provide first and second multiplied signals, a combining circuit responsive to the first and second multiplied signals for generating a density signal having a pulse density proportional to the frequency of the input signals, a d

Abstract: A phase-locked loop frequency synthesizer has a charge pump, phase-locked loop filter, voltage-controlled oscillator, and a bandwidth calibration circuit. The bandwidth calibration circuit measures the gain of the voltage-controlled oscillator and uses the measured voltage-controlled oscillator gain to adjust the charge pump level. The charge pump level is adjusted so that a product of the voltage-controlled oscillator gain and the measured charge pump level results in a constant phase-locked loop bandwidth.

Abstract: A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for executing timing-sensitive instructions. The timing and event processor includes a plurality of instruction sequencers for executing timing-sensitive instruction threads and a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.

Abstract: A bipolar differential output circuit includes an input differential bipolar stage for receiving an input signal and generating a differential output current. An output differential pair of bipolar transistors without a bipolar tail current source responds to the input signal by providing a representative output signal. And a current mirror circuit passes current from the input differential pair to the output differential pair.

Abstract: A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for executing timing-sensitive instructions. The timing and event processor includes a plurality of instruction sequencers for executing timing-sensitive instruction threads and a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.

Abstract: A bandgap voltage reference circuit is provided that includes a PTAT source whose polarity reverses at a determinable temperature. The PTAT source is combined with a CTAT source in a manner to remove the effects of the slope of the CTAT source such that a voltage reference may be generated. A method of operating such a circuit is also described.

Abstract: A transceiver system is disclosed for use in a telecommunication system. The transceiver system includes a transmission circuit with a differential transmitter input coupled via a transmitter input stage to a differential input of a transmission amplifier in an embodiment. The transmitter input stage includes a trimmable resistor, one end of which is coupled to a positive transmit input signal, and the other end of which is coupled to a negative transmit input signal. The transceiver system also includes a receiver circuit with a differential receiver output coupled to a differential input of a receiver amplifier, and further includes a transmission line interface circuit coupled to a differential output of said transmission amplifier and to a differential input of said receiver amplifier. In accordance with other embodiments, the receiver amplifier includes an input stage that includes a first plurality of capacitors and a feedback circuit that includes a second plurality of capacitors.

Abstract: The present invention relates to a method and system for reducing integral non linearity errors in a pipeline Analog to Digital Converter (ADC). The invention provides in a first embodiment a method comprising the steps of: adding an analog dither signal to the analog input signal of a pipeline Analog to Digital Converter, and converting the analog input signal to a digital output signal by means of the pipeline Analog to Digital Converter. The amplitude of the analog dither signal is determined by the architecture of the Analog to Digital Converter. The invention also provides in a second embodiment a circuit comprising a pipeline analog to digital converter for converting an analog input signal to a digital output signal and a feedback circuit coupled to the converter such that the digital output signal is adapted to have an average non linearity error value of about zero LSBs.

Abstract: A coupling apparatus allows anti-phase movements of inertial sensor element frames along parallel axes but substantially prevents in-phase movements of the frames. The coupling apparatus includes a bar coupled between first and second sensor element frames and at least one supporting structure supporting the bar. The at least one structure is coupled to a substrate underlying the frames. The structures allow the bar to rotate at a pivot point when the frames move in anti-phase to one another along substantially parallel axes but substantially prevent in-phase movements of the frames.

Abstract: A method for one-way coupling an input signal to an integrated circuit on a semiconductor chip with the integrated circuit electrically isolated from the input signal comprises forming a MOS isolation coupler on the semiconductor chip by a CMOS process. The MOS isolation coupler comprises an inductor coil for generating a magnetic field in response to an input signal applied to terminals thereof. A MAGFET having a split drain formed by respective drain portions is formed on the semiconductor chip below the inductor coil, so that a current difference is induced between the drain currents in the drain portions which is proportional to the strength of the magnetic field generated by the inductor coil resulting from the input signal. The MAGFET is formed prior to the inductor coil. An oxide isolating layer is provided over the MAGFET, and the inductor coil is formed on the oxide layer.

Abstract: A reduced complexity turbo decoding scheme combines elements from two MAP (Maximum a posteriori) algorithms, namely a LogMAP algorithm and a max-LogMAP algorithm. Forward and backward recursive metrics are computed in accordance with the max-LogMAP algorithm, while output extrinsic LLR (Log Likelihood Ratio) values are computed in accordance with the LogMAP algorithm.

Abstract: A die has a part that is sealed with a cap. The seal can be hermetic or non-hermetic. If hermetic, a layer of glass or metal is formed in the surface of the die, and the cap has a layer of glass or metal at a peripheral area so that, when heated, the layers form a hermetic seal. A non-hermetic seal can be formed by bonding a cap with a patterned adhesive. The cap, which can be silicon or can be a metal paddle, is electrically coupled to a fixed voltage to shield the part of the die.

Abstract: The present application relates to the manufacture of Wafer Level Chip Scale Packages (WLCSPs), which are a type of CSP in which the traditional wire bonding arrangements are dispensed with in favour of making direct contact by means of conductive bumps (typically solder balls) to the integrated circuitry. WLCSPs differ from fine pitch Ball Grid Array (BGA) and leadframe based Chip Scale Packages (CSPs) in that most of the packaging process steps are performed at wafer level. A package and method of manufacture are provided which prevent the ingress of light to the internal circuitry of WLCSP packages by providing a substantially opaque coating on the inactive side of the WLCSP packages and at least partially on the sides of WLCSP packages.