Abstract: A receiver architecture for processing spread spectrum signals. The receiver has an RF front end to receive and down convert a broadcast signal to an intermediate frequency carrier. The IF signal is digitized and provided to a processor (which may be a software-driven DSP, an ASIC or other embodiment) for processing. A given IF carrier is removed and the signal is low pass filtered. The signal is provided to a number of channels, each, for example, correspond to a unique transmitter. On each channel the sample rate is reduced to a predetermined fixed rate with timing mismatch compensated. The Doppler frequency shift, as estimated for the channel, is removed succeedingly. A locally generated copy of the spreading code used by the transmitter is applied to the carrier and Doppler removed signal at the predetermined fixed sample rate. The de-spread signal is used to provide estimates of the Doppler shift and for subsequent sample selection.

Abstract: A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.

Abstract: Automatic power saving for decreasing power demand during a power interruption while maintaining the appearance of full operation of a signal processor including predefined power consuming circuits, a communications interface, and a state machine includes sensing when a power supply interruption has occurred, providing a clock signal, halting the clock signal to the predefined power consuming circuits during a power interruption; and continuing to provide a clock signal to a communications interface regardless of a sensed interruption for maintaining the appearance of normal operations during the sensed interruption.

Abstract: MEMS in-plane resonators include a substrate wafer, at least one resonant mass supported by the substrate wafer and configured to resonate substantially in-plane, and at least one transducer coupled to the at least one resonant mass for at least one of driving and sensing in-plane movement of the at least one resonant mass, wherein at least part of one surface of the resonant mass is configured for exposure to an external environment and wherein the at least one transducer is isolated from the external environment. Such MEMS in-plane resonators may be fabricated using conventional surface micromachining techniques and high-volume wafer fabrication processes and may be configured for liquid applications (e.g., viscometry, densitometry, chemical/biological sensing), gas sensing (e.g., where a polymer film is added to the sensor surface, further degrading the damping performance), or other applications.

Abstract: A dual backplate MEMS microphone system including a flexible diaphragm sandwiched between two single-crystal silicon backplates may be formed by fabricating each backplate in a separate wafer, and then transferring one backplate from its wafer to the other wafer, to form two separate capacitors with the diaphragm.

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Abstract: Aspects of the present invention provide apparatuses and methods to provide slew rate enhancement during an initial stage of operation of an amplifier and processing of an input signal with low noise introduction during a subsequent amplification stage of operation. During the initial stage, a high bandwidth component of the amplifier can be engaged to provide slew rate enhancement of the overall amplifier. The adaptive slew rate enhancement can be based on a detected imbalance of an output of a low bandwidth component of the amplifier. Once a desired operating state of the amplifier is achieved, the high bandwidth component can be disengaged. The low bandwidth component can then solely operate on a received input signal during the amplification stage. The low bandwidth component can be low power and can introduce low levels of noise, thereby ensuring minimal noise introduction and corruption of the amplified output signal of the amplifier.

Abstract: A computer program for creating a computer program executable on one or more digital signal processors each having a predefined function set. The computer program includes computer code for receiving user input selecting one or more digital signal processors. The computer program also includes computer code for defining one or more audio digital signal processing graphical controls. Each graphical control has an associated interface handler. The computer program also has computer code for associating an algorithm module containing digital processor specific functionality with the one or more audio graphical controls using the interface handler and computer code for linking the one or more audio graphical controls together defining an execution path.

Abstract: A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.

Abstract: Apparatus and methods are disclosed, such as those involving an RF receiver. One such apparatus includes a front end having an input and an output. The front end forms part of an RF signal receive path. The front end includes a front-end resistor configured to receive an input signal; and a passive mixer downstream of the front-end resistor on the receive path. The passive mixer mixes the input signal with a local oscillation signal. The front-end includes a transimpedance amplifier located downstream of the passive mixer on the receive path. The transimpedance amplifier includes an input and an output. The front end further includes a feedback resistor coupled between the input and output of the transimpedance amplifier. The gain of the front end is a ratio of the feedback resistance to the front-end resistance, and is temperature- and frequency-insensitive. The apparatus also provides relatively constant input impedance and high linearity.

Abstract: Switching voltage regulator embodiments are provided with hysteretic control to thereby switch between pulse-width modulation and pulse-frequency modulation operational modes. The switching is in response to different levels of an error voltage Verr in the feedback loop of voltage regulators. The hysteretic control is configured to provide a dc hysteretic response to changes in the error voltage Verr and also an ac hysteretic response to these changes. These two responses can be independently set to thereby enhance operational speed of the voltage regulators and also enhance immunity to transient noise signals that are generated by the mode switching. The voltage regulator embodiments facilitate instant return from the pulse-frequency modulation operational mode to the pulse-width modulation operational mode so that the stability of the feedback control of the regulator is enhanced.

Abstract: A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a pulsed, substantially-random signal into a plurality of channels in the ADC. After the substantially-random signal is injected, a gain correlation value is determined for each channel, which value indicates a degree of correlation between the injected substantially-random signal and an output of the respective channel. The gain correlation values are then compared to determine a degree of mismatch between the channels. At least one of the channels is calibrated as a function of the determined degree of mismatch.

Abstract: Multiplication engines and multiplication methods are provided for a digital processor.

Abstract: An apparatus and method for determining characterizing attributes of an actuator is provided. An actuator may be moved to a maximum capacitance position. At the maximum capacitance position, an initial measurement of the actuator capacitance is made. The actuator is moved a predetermined increment toward a first extreme position, and the actuator capacitance is again measured. If the capacitance changed by a threshold amount, the signal preceding the signal that caused the actuator to move is recorded as an approximate response curve end point, or the first extreme position. The actuator is again moved a predetermined increment toward a second extreme position. After each move, the capacitance is measured. If it is determined the capacitance did change by a threshold amount from the previously measured capacitance, the signal related to the previously measured capacitance is recorded as an approximate response curve end point, or the second extreme position.

Abstract: DC-DC voltage converter systems are provided in which a switching voltage converter is arranged with an inductor to switch first and second currents with duty cycles D and D? determined by an error voltage Verr to thereby maintain an output voltage Vout. A transconductance amplifier having an amplifier output provides the error voltage Verr in response to the output voltage and a reference voltage Vref. A ripple current Irpl is provided to the amplifier output in response to the difference between the error voltage Verr and a clamp voltage Vclmp. Finally, a current comparator generates a skip signal to turn off the first and second currents in response to a selected threshold of the ripple current. In this process, the ripple current Irpl substantially clamps the error voltage Verr to the clamp voltage Vclmp.

Abstract: A clock generator is disclosed for use with an oscillator device. The clock generator may include a signal conditioning pre-filter and a comparator. The signal conditioner may have an input for a signal from the oscillator device, and may include a high pass filter component and a low pass filter component. The high pass filter component may pass amplitude and frequency components of the input oscillator signal but reject a common mode component of the oscillator signal. Instead, the high pass filter component further may generate its own common mode component locally over which the high frequency components are superimposed. The low pass filter component may generate a second output signal that represents the locally-generated common mode component of the first output signal. The clock generator may have a comparator as an input stage which is coupled to first and second outputs of the filter structure.

Abstract: An adaptive phase offset controller for use with a switching power converter having first and second channels. The controller includes a discriminator which detects a ‘critical condition’ in which a switching signal for the first channel transitions during a critical time interval so as to give rise to crosstalk that can corrupt the operation of the second channel's control circuit. When the discriminator detects a critical condition, a phase offset circuit offsets the phase of the first channel's switching signals, such that subsequent transitions occur outside of the critical time interval. A second discriminator and phase offset circuit are preferably employed to detect critical conditions which can give rise to crosstalk that can corrupt the operation of the first channel's control circuit.

Abstract: A negative resistance device for a multiphase oscillator is disclosed. The negative resistance device is coupled to taps of the multiphase oscillator so that it injects no energy into the oscillator when the oscillator is most sensitive to noise, thereby decreasing the phase noise of the oscillator. The negative resistance device also guarantees the direction of movement of a traveling wave past the taps of the multiphase oscillator.

Abstract: The invention is directed to a digital isolation system including an isolation barrier, a transmitter circuit receiving an input signal and transmitting a positive pulse upon detecting a first type of edge in the input signal and transmitting a negative pulse upon receipt of a second type of edge in the input signal and a receiver circuit receiving the transmitted signals, removing noise in the received signal and reconstructing the input signal using a differential comparator.

Abstract: Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an actively-controlled protection circuit includes a detector, a timer, a current source and a latch. The detector is configured to generate a detection signal when the detector determines that a transient signal satisfies a first signaling condition. The timer is configured to receive the detection signal, and to generate a current control signal. The current control signal is provided to a current source, which produces a trigger current at least partly in response to the control signal. The trigger current is provided to a node of the latch, thereby enhancing the conductivity modulation of the latch and selectively controlling the activation voltage of the latch.