Abstract: A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

Abstract: A bandgap voltage reference is described which has reduced sensitivity to noise and amplifier offset. By configuring the circuitry such that the base width of the component transistors is not varied on application of a bias, it is possible to obviate the Early effect.

Abstract: A circuit with a common-mode dual output includes a feedback circuit connected to alternate the states of the dual output between an average output level and a desired common-mode level. The difference between the average and desired levels is proportional to a signal offset level. An impedance matching circuit is connected to the feedback circuit to adjust the signal offset level.

Abstract: Digital filters are provided that include a converter and a data processor. The converter converts successive strings of M successive data elements that occur at a system rate Fs in an input data stream Din to M parallel data elements that respectively occur at a substream rate Fs/M in M data substreams Dsbstrm. At a reduced substream rate Fs/M, the processor generates M convolutions of the filter's quantized impulse response with the M data substreams wherein each of the convolutions is arranged to generate a different one of M successive filtered output signals. Because the convolutions are conducted at the reduced substream rate Fs/M, the filters can operate at increased system rates. Preferably, the digital filter also includes a multiplexer that selects, at the system rate Fs, the M filtered output signals in successive order to thereby form a filtered output data stream Dout.

Abstract: A method converts an input data rate associated with N units of data to an output data rate associated with M units of data. The method includes calculating N write-control parameters each associated with one of M addresses of an output memory, directing each of N values of input data to an associated address of the output memory in response to the N calculated write-control parameters, and reading the output memory to provide output data associated with the output data rate. If N is greater than M, some of the N write-control parameters are associated with at least one shared address of the M addresses. If M is greater than N, all of the N write-control parameters are associated with different addresses of the M addresses. An apparatus is configured to implement this method.

Abstract: An optical cross-connect switch comprises a base (216), a flap (211) and one or more electrically conductive landing pads (222) connected to the flap (211). The flap (211) has a bottom portion that is movably coupled to the base (216) such that the flap (211) is movable with respect to a plane of the base (216) from a first orientation to a second orientation. The one or more landing pads (222) are electrically isolated from the flap (211) and electrically coupled to be equipotential with a landing surface.

Abstract: A switched current temperature sensing circuit (1) comprises a measuring transistor (Q1) which is located remotely of a measuring circuit (5) which applies three excitation currents (I1,I2,I3) of different values to the measuring transistor (Q1) in a predetermined current sequence along lines (10,11). Resulting base/emitter voltages from the measuring transistor (Q1) are applied to the measuring circuit (5) along the same two lines (10,11) as the excitation currents are applied to the measuring transistor (Q1). Voltage differences ?Vbe of successive base/emitter voltages resulting from the excitation currents are integrated in an integrating circuit (36) of the measuring circuit (5) to provide an output voltage indicative of the temperature of the measuring transistor (Q1).

Abstract: A novel circuit is used to monitor the common-mode voltage at the summing junctions of the first integrator in a continuous-time ?? ADC, wherein the circuit produces a control voltage which adjusts the quiescent current of the feedback DAC to compensate for any common-mode offset current. Since the adjustment takes place within the feedback DAC, there is no extra noise added to the differential signal path. The implementation provides for no degradation to the SNR of the converter.

Abstract: A charge pump circuit is disclosed that includes a positive current output circuit for providing a positive current to an output of the charge pump circuit, a negative current output circuit for providing a negative current to the output of the charge pump circuit, and a calibration unit for permitting the charge pump circuit to be adjusted to reduce any current mismatch between the positive and negative currents and to provide that any current mismatch is integrated into a PLL loop filter capacitance.

Abstract: A circuit is provided which is adapted to compensate for the inherent parasitic capacitance which is implicit in switched capacitor circuits. By shielding the parasitic capacitance to a common node of the circuit and then connecting this shield to a voltage source that tracks the voltage change at the input to an amplifier, the present invention provides a bootstrapping effect that enables a minimization of the effect of the parasitic capacitance. The invention also provides a circuit that is adapted to compensate for curvature in the output of a switched capacitor bandgap reference.

Abstract: Methods and apparatus for accessing flash memory in a continued burst mode are provided. The apparatus includes a processor for executing instructions including memory access instructions, the processor generating a next access signal that indicates if a next memory access is in sequence with a current memory access, a memory having a continued burst mode of operation, and a bus interface for controlling access to the memory in response to the memory access instructions. The bus interface unit enables the continued burst mode of the memory while the next access signal is asserted.

Abstract: An indirect variable frequency synthesiser for synthesising selectable frequencies from a reference frequency including a multi-divisor programmable frequency divider located in a feedback loop of the frequency synthesiser for dividing the feedback frequency in the feedback loop, the divider being responsive to a varying control signal applied thereto representative of a rational number of selectable value for selecting the divisor thereof for fractional division of the feedback frequency. A variable modulus interpolator converts a fractional part of the rational number of selectable value to a varying digital code representative of the fractional part of the rational number.

Abstract: A power converter provides power across an isolation barrier, such as through the use of coils. A coil driver has transistors connected in a positive feedback configuration and is coupled to a supply voltage in a controlled manner by measuring the output power and opening or closing a switch as needed between the power supply and the coil driver. An output circuit, such as a FET driver, can be used with or without isolation to provide power and a logic signal.

Abstract: A method for monitoring the performance of a test apparatus (1) for testing a batch of integrated circuits. The apparatus 1 comprises a test site 2 in which the integrated circuits are sequentially tested, and a microprocessor (4) for carrying out the appropriate tests on the integrated circuits. A first ROM (5) stores a computer programme for controlling the operation of the microprocessor (4) for carrying out the tests, and a first RAM (10) stores a computer programme for controlling the operation of the microprocessor (4) for monitoring the performance of the test apparatus (1). In particular, the computer programme stored in the first RAM (10) operates the microprocessor (4) for computing the test time period for each integrated circuit tested, and also for computing the intervening time periods between each integrated circuit tested. The intervening time periods between the respective test time periods are classified as either first or second category delays or index time periods.

Abstract: An RMS-to-DC converter implements the difference of squares function using two squaring cells operating in opposition to attain a balance. Each of the squaring cells is implemented as a grounded-base transistor and a two-transistor current mirror. The emitter of the grounded-base transistor is coupled to the input terminal of the current mirror at a node which receives the input signal. The collector of the grounded-base transistor and the output of current mirror are coupled together to generate an output current having a square-law relationship to the input signal. One of the squaring cells receives the input signal and operates at high frequencies (HF), while the other receives a feedback signal and operates in a quasi-DC mode. In a measurement node, a nulling circuit closes a feedback loop around the DC squaring cell to null the output currents from the squaring cells.

Abstract: A transceiver system is disclosed for use in a telecommunication system. The transceiver system includes a transmission circuit including a differential transmitter input coupled to a differential input of a transmission amplifier, a receiver circuit including a differential receiver output coupled to a differential output of a receiver amplifier, and a transmission line interface circuit that is coupled to a differential output of the transmission amplifier and to a differential input of the receiver amplifier. The transmission line interface circuit providing a second order high pass transfer function.

Abstract: A center focussed SIMD array system including an SIMD array including a plurality of processing elements arranged in a number of columns and rows and having two mutually perpendicular axes of symmetry defining four quadrants; and a sequencer circuit for moving the data in each element to the next adjacent element towards one axis of symmetry until the data is in the elements along the one axis of symmetry and then moving the data in the elements along the the one axis of symmetry to the next adjacent element towards the other axis of symmetry until the data is at the four central elements at the origin of the axes of symmetry.

Abstract: A circuit and method are provided to enable the synchronization of an on-demand, synchronous signal with an asynchronous signal. The synchronous signal is activate only for a portion of the period of the asynchronous signal, thus providing beneficial power conservation. The synchronous signal is activated in response to a first edge of the asynchronous signal, and deactivated in response to a second edge of the asynchronous signal.

Abstract: A novel optical path switching system, architecture and technique wherein light beam data traffic is to be switched by MEMS mirrors between source and destination nodes, and test ports are used to set up optical paths even before the real data traffic is propagated, with a combination of an electrical mirror-sensing feedback loop for controlling coarse mirror positioning, and an optical path power-sensing feedback loop for controlling fine adjustments in the mirror position.

Abstract: A first device comprises a loop circuit to control a sample rate of a digital circuit element. A circuit comprises a digital loop circuit to control a sample rate of a digital circuit element to be a function of a frequency of a signal received by the circuit. A second device receives two or more sampled data streams having sample rates different from one another, converts the sample rate of one or more of the data streams to provide two or more data streams having sample rates compatible with one another, and combines the two data streams. Sample rate converter devices are used in a PLL and a clock recovery circuit.