Abstract: Signal converters are provided that accurately process dc-coupled source signals in the presence of different predetermined voltage and current source requirements. Processing structures are described that satisfy these requirements while providing accurate control of common mode levels along a processing path and accurate reduction of converter offset errors.

Abstract: A read-write interface system and method for a peripheral device includes storing data to be processed by a peripheral device; receiving a set of input data bits; transferring the set of input data bits from the shift register to the latch circuit in a write operation; accessing a leading bit of the set of input data bits from the latch circuit in advance of a read operation; and enabling in a read operation the rest of the input data bits in the latch circuit to be transferred to the shift register to be output with the leading bit.

Abstract: A temperature sensor circuit is provided which is adapted to provide an indication of the temperature on a chip. The sensor includes a bandgap temperature sensor which is sequentially driven by a plurality of current sources. The current sources are shuffled so as to minimize problems associated with matching currents.

Abstract: A switched capacitor buffer operating by the push-pull method is taught. The buffer may include a pull-up device and a pull-down device. A switched capacitor circuit may be used to control the pull-up device and the pull-down device to achieve accurate push-pull operation. According to some embodiments, the switched capacitor buffer displays an optimal combination of design simplicity, low power consumption and high-frequency response.

Abstract: A system and apparatus for testing a micromachined optical device includes a computerized test station that generates signals to control the micromachined optical device as well as various test equipment and analyzes signals generated by the micromachined optical device and various test equipment. The computerized test station typically provides for both manual and automated testing of the micromachined optical device. In order to test the micromachined optical device, various optical measurement devices are typically mounted on a frame. The frame is configured so as to maintain proper alignment between the optical measurement devices and the micromachined device under test. The frame is mounted to or integral with a focusing device. The frame moves along with focusing movements of the focusing device in such a way that the optical measurement devices are properly aligned with the micromachined device under test when the focusing device is focused on the micromachined device under test.

Abstract: Bias controllers are provided which alter a bias control signal so that a bias signal (e.g., a current signal) of an electronic network rapidly responds to increases in the rate-of-change of the network's analog input signal. This enhances the linearity of a system that includes the electronic network. Subsequent decreases in the rate-of-change are sensed and a decrease of the bias control signal is then paced at a rate selected to ignore short-term rate-of-change variations (e.g., modulation variations) but follow longer-term rate-of-change reductions to thereby enhance system efficiency without sacrificing system linearity.

Abstract: In parallel with accesses to a cache made by a core processor, a DMA controller is used to pre-load data from a main memory into the cache. In this manner, the pre-load function can make the data available to the processor application before the application references the data, thereby potentially providing a 100% cache hit ratio since the correct data is pre-loaded into the cache. In addition, if a copy-back cache is employed, the cache memory system can also be configured such that processed data can be dynamically unloaded from the cache to the main memory in parallel with accesses to the cache made by the core processor. The pre-loading and/or post unloading of data may be accomplished, for example, by using a DMA controller to burst data into and out of the cache in parallel with accesses to the cache by the core processor. This DMA control function may be integrated into the existing cache control logic so as to reduce the complexity of the cache hardware (e.g.

Abstract: In one embodiment, techniques are disclosed for causing a programmable processor to process one instruction at a time. Single-step debugging may be performed by taking an exception after each instruction or by invoking emulation mode after each instruction. The particular single-step debugging technique may be based upon state of control bits, or may be based upon the processor's current mode of operation, or both.

Abstract: A voltage multiplier has a first stage that multiplies an input voltage, and a second stage that multiplies the output of the first stage. To that end, the voltage multiplier has the noted first stage having an input to receive the input voltage, and the second stage in series with the first stage. As noted above, the first stage is capable of multiplying the input voltage by a first amount to produce a first stage output voltage. The second stage thus has an input to receive the first stage output voltage. After receipt, the second stage is capable of multiplying the first stage output voltage by a second amount to produce a second stage output voltage.

Abstract: A voltage regulator includes a linear mode regulator having a high pass filter circuit connected between its output and an output node, and a switch mode regulator having an low pass filter circuit connected between its output and the same output node. The high pass filter passes high frequency AC current provided by the linear mode regulator to the output node and reduces the low frequency AC and DC currents to substantially zero, and the low pass filter prevents the high frequency AC current produced by the linear mode regulator from being drawn by the switch mode regulator and passes the low AC and DC currents provided by the switch mode regulator to the output node. Thus, the present regulator offers the high response speed and low noise of a linear mode regulator, and the high power efficiency and large continuous output current capability of a switch mode regulator.

Abstract: A multi-channel integrated circuit comprises a plurality of channels (CH1 to CH20). A DAC (3) is provided in each channel (CH1 to CH20) for converting digital data inputted to the circuit (1) through an I/O port (14). Digital data to be converted by the DACs (3) is selectively applied to input registers (10) of each channel (CH1 to CH20) on a digital data bus (16) under the control of an interface and control logic circuit (15). The digital words written to the input registers (10) are in turn written to DAC registers (9) through corresponding digital switches (12) for conversion by the DACs (3). A clear code register (22) stores a clear code for writing to the DAC registers (9) in response to a clear signal applied to a clear terminal (24) of the circuit (1) so that analogue outputs appearing on output terminals (5) of the channels (CH1 to CH20) are of a predetermined value, typically, zero volts, when the circuit (1) is set in a clear condition.

Abstract: A programmable input voltage range analog-to-digital converter in which a split gate oxide process allows the use of high voltage (±15 volt) switches on the same silicon substrate as standard sub-micron 5 volt CMOS devices. With this process, the analog input voltage can be sampled directly onto one or more sampling capacitors without the need for prior attenuation circuits. By only sampling on a given ratio of the sampling capacitors, the analog input can be scaled or attenuated to suit the dynamic range of a subsequent ADC. In the system of the present invention, the sampling capacitor can be the actual capacitive redistribution digital-to-analog converter (CapDAC) used in a SAR ADC itself, or a separate capacitor array. By selecting which bits of the CapDAC or separate sampling array to sample on, one can program the input range.

Abstract: A proportional to absolute temperature voltage circuit. A voltage circuit including a first amplifier having first and second inputs and having an output driving a current mirror circuit is provided. Outputs from the current mirror circuit drive first and second transistors which are coupled to the first and second input of the amplifier respectively. The base of the first transistor is coupled to the second input of the amplifier and the collector of the first transistor is coupled to the first input of the amplifier such that the amplifier keeps the base and collector of the first transistor at the same potential. The first and second transistors are adapted to operate at different current densities such that a difference in base emitter voltages between the first and second transistors may be generated across a resistive load coupled to the second transistor, the difference in base emitter voltages being a PTAT voltage.

Abstract: Timing enhancements of embodiments of the invention are realized in time-interleaved converter systems with minimal network additions that facilitate the insertion of a timing signal into the system's input analog signal. The timing signal travels with the input analog signal so that it continues to accurately define predetermined sample times in the analog signal even as they travel over different path lengths to individual converters. Each converter has a feedback path which adjusts the timing of that converter's samples with a correction signal whose value is determined by contributions of first and second different amplitudes of the timing signal to that converter's output signals.

Abstract: A memory system and a method for operating a memory system are provided. The memory system includes a set of memory banks, logic for calculating a first address in each memory bank from the set of memory banks and a controller receiving a transfer address from a computing device. The controller includes logic for selecting a memory bank from the set of memory banks based on the transfer address and the first addresses of the memory banks, and for mapping the transfer address to a target address in the selected memory bank based on a first address in the selected memory bank. As a result, the set of memory banks has a contiguous memory space.

Abstract: Efficient re-computation of an error detection code is achieved with an original data message that includes a payload and an error detection code. The error detection code comprises a value determined according to an error detection formula using the payload. The payload is modified using a payload transformation formula. The error detection code is re-computed from the original error detection code, rather than from the modified payload. The formula for re-computing the error detection code is different from the formula used to originally obtain the error detection formula, and does not use the original payload or the modified payload.

Abstract: Methods and apparatus are provided for operating an embedded processor system that includes a processor and a cache memory. The method includes filling one or more lines in the cache memory with data associated with a first task, executing the first task, and, in response to a cache miss during execution of the first task, performing a cache line fill operation and, during the cache line fill operation, executing a second task. The cache memory may notify the processor of the line fill operation by generating a processor interrupt or by notifying a task scheduler running on the processor.

Abstract: A micromachined device has a body suspended over a substrate and movable in a plane relative to the substrate. The body has a perimeter portion, a first cross-piece portion extending from one part of the perimeter portion to another part of the perimeter portion to define at least first and second apertures, a first plurality of fingers extending along parallel axes from the perimeter portion into the first aperture, and a second plurality of fingers extending along parallel axes from the perimeter portion into the second aperture.

Abstract: A voltage level translator provides an output signal having an external voltage in response to an input signal having an internal voltage. The voltage level translator includes first and second input signal transistors, first and second output signal transistors, and includes a signal stabilization circuit and/or an enable circuit. A ready-signal generation circuit provides a ready signal indicating that a voltage supply is at an operating voltage. The ready-signal generation circuit can include unbalanced transistors.

Abstract: The proposed technique uses basic properties of a Huffman codebook to decode a coded data bit stream having a plurality of variable length codewords based on the Huffman codebook. This is achieved by sorting codewords in the Huffman codebook based on potential values. The potential values are computed using the basic parameters of the codewords in the Huffman codebook. A current bit sequence having a predetermined length is extracted from the coded data bit stream. A potential value of the extracted bit sequence is then computed using the basic parameters of the codewords in the Huffman codebook. The sorted Huffman codebook is then searched to find a computed potential value in the sorted Huffman codebook that is substantially close to the computed potential value of the extracted bit sequence. The extracted current bit sequence is decoded based on the outcome of the search.