Abstract: An improved voltage scaling DAC responsive to an N-bit input code word having M LSBs including first and second outer impedance string segments, each comprising 2N−M−1 series-connected impedances of substantially equal value, an inner string of series-connected impedances of substantially equal value having first and second end points, first and second outer string switch networks providing electrical connections between selected outer string impedance terminals and first and second common nodes, and an inner string switch network providing electrical connection between selected inner string impedance terminals and an output node. The inner string of series-connected impedances comprises no more than 2M−1 impedances of substantially equal value. A method for adjusting the gain of a voltage scaling DAC is also described.

Abstract: A control circuit (10) controls the operation of a laser diode (1) for controlling the average power output (Pav) and the extinction ratio. A state machine (21) controls the control circuit (10) which reads the current from a monitor photo diode (2) which is coupled to the laser diode (1). An amplifier (20) determines the average power output of the laser diode (1) which is fed to a first comparator (23). The first comparator (23) compares the average power output with a reference value set by a resistor (R3). The output from the comparator (23) is fed to the up/down pin of a first counter (25) which is clocked by the state machine (21). In the event that the average power output is too high the first counter (25) decreases the bias current to the laser diode (1) outputted by a constant current source (5), and vice versa.

Abstract: Comparator methods and structures are provided whose accuracy in analyzing an output signal Sout of a DUT is enhanced because they compensate for a signal distortion that is imposed by a transmission path over which the output signal Sout is received. The methods include the steps of a) providing a reference signal Sref; b) combining the reference signal Sref with a reference distortion that corresponds to the signal distortion to thereby realize a compensated reference signal Scmp-ref; and c) comparing the output signal Sout to the compensated reference signal Scmp-ref to determine signal parameters of the output signal Sout. The methods of the invention facilitate the use of simple comparator structures that do not significantly increase the cost of automatic test equipment but which do significantly increase accuracy of signal analysis.

Abstract: A detector circuit (1) for detecting the presence or absence of a television (2) on an output (3) of a video DAC (4) comprises a comparator (11) for comparing a voltage developed by the video signal on a control resistor R2 with a reference voltage of 0.5 volts. The resistor R2 is of 75 ohms and matches the internal impedance R1 of 75 ohms of the television (2). A latch (12) latches the output from the comparator (11) onto an output pin Q when the voltage developed across the control resistor R2 is developed by an equalisation pulse of the vertical blanking interval of the video signal. In the presence of a television (2) the voltage developed across the control resistor R2 is 0.35 volts, which pulls the output of the comparator (11) low, while in the absence of a television (2) the voltage developed across the control resistor R2 is 0.7 volts which pulls the output of the comparator (11) high.

Abstract: In one embodiment, a programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The first and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.

Abstract: In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline, and a second pipeline. Furthermore, the processor may include a control unit adapted to efficiently implement the hardware when performing a hardware loop.

Abstract: In one embodiment, a method is disclosed for holding instruction fetch requests of a processor in an extended reset. Fetch requests are disabled when the processor undergoes a reset. When the reset is completed, fetch requests remain disabled when the instruction memory is being loaded. When loading of the instruction memory is completed, fetch requests are enabled.

Abstract: In one embodiment, a programmable processor is adapted to include a speculative count register. The speculative count register may be loaded with data associated with an instruction before the instruction commits. However, if the instruction is terminated before it commits, the speculative count register may be adjusted. A set of counters may monitor the difference between the speculative count register and its architectural counterpart.

Abstract: A digital radio tuner lock detector receives an in-phase (I) data signal and a quadrature (Q) data signal. The lock detector processes these signals to compute a data signal power estimate and integrates the data signal power estimate to provide a threshold signal value. The lock detector also includes a carrier frequency lock detector and a carrier phase lock detector. The carrier frequency lock detector receives the I and Q data signals and computes a frequency error signal and integrates the frequency error signal to provide an integrated frequency error signal. The carrier frequency lock detector compares the magnitude of the integrated frequency error signal to the threshold signal value to determine if frequency lock has been achieved and provides a frequency lock status signal indicative thereof. The carrier phase lock detector receives the I and Q data signals and computes a phase error signal and integrates the phase error signal to provide an integrated phase error signal.

Abstract: A circuit protects differential inputs of circuitry, such as RF circuitry, against electrostatic discharge. The circuit includes first and second diodes connected in opposite directions between a first differential input pin and a virtual ground node, third and fourth diodes connected in opposite directions between a second differential input pin and the virtual ground node, a first protection device connected between the virtual ground node and a first external pin, such as a positive supply pin, and a second protection device connected between the virtual ground node and a second external pin, such as a negative supply pin. The first and second protection devices may be fifth and sixth diodes, respectively. Because no signal appears at the virtual ground node, the fifth and sixth diodes can be relatively large.

Abstract: Quasi-differential successive-approximation methods and structures are provided for converting analog signals into corresponding digital signals. These methods and structures realize the signal-to-noise improvements of fully-differential SAR ADCs and the calibration accuracy improvements of pseudo-differential SAR ADCs. Structures of the invention operate in a fully-differential mode to establish more-significant bits of the corresponding digital signals and in a pseudo-differential mode to establish the less-significant bits.

Abstract: A variable gain amplifier has at least two branches connected in parallel to drive a common output load. Each branch includes at least two FETs in a cascode configuration. A first FET in each branch is arranged to receive an input signal and to amplify the signal in a common source configuration; the second FET is arranged in a common gate configuration with its source receiving the output current of the first FET. The gate of the second FET is coupled to a corresponding gain control input so that the second FET is enabled when the gate receives an enabling gain control signal and disabled otherwise. Preferably the first and second FETs in each branch are biased in a saturation region of operation when the second FET is enabled by the gain control input. This maintains a low distortion figure throughout the dynamic range of the gain control. Preferably, the invention also includes an active fixed gain power amplification stage for coupling the output to a power amplifier.

Abstract: An analog-to-digital converter including a quantizer and a residue generator, both of which sample an input voltage in parallel. The sampling characteristics of each of the residue generator and the quantizer are designed to substantially match one another. This converter may be used as a low-power ADC front-end circuit that does not require a dedicated sampleand-hold circuit. The front-end circuit consists of two substantially-matched sampling networks, one for the residue generator and the other for the quantizer, inside the first stage of the converter.

Abstract: A resistive DAC (1) comprises a digital input port (2) and an analog output port (3) on which analog resistance output values are outputted in response to corresponding digital input codes on the input port (2). A decoding and control circuit (4) selects appropriate resistors (R1) to (RN) from a resistor chain (5) for providing the analog resistance output of the analog output port (3). A register (7) stores a transfer coefficient in binary code which can be read through the input port (2) and by which each digital input code should be multiplied in order to produce an analog resistance output of predetermined value. The transfer coefficient in the register (7) takes account of variations in internal circuit parameters which causes the analog resistance outputs on the output port (3) to be less than they would in an ideal resistive DAC.

Abstract: A micromechanical, dithered device comprising a substrate, a movable mass connected to the substrate by a suspension, a position sensor, a dither signal generator, a dither force transducer connected between the substrate and the movable mass, the input of the dither force transducer being connected to the output of the dither signal generator and a calculator taking as inputs at least the position sensor output and the dither signal generator output. In one embodiment of the invention, the dithered device includes an electrostatic force transducer for applying feedback. In this embodiment, dither force may be directly applied to the mechanical proof-mass utilizing electrostatic structures similar to electrostatic structures used for feedback. The electrostatic dithering structures provide good matching between the feedback and dither electrodes, enabling the use of simple logic for subtraction of the dither signal from the accelerometer output.

Abstract: A multiprocessor system includes a distributed bus arbitration system in which bus arbitration takes place simultaneously on each of the multiple processors connected to the bus. Each processor has a local arbitrator of common configuration with the other local arbitrators and a dedicated request line. Each local arbitrator is connected to each dedicated request line to monitor signals on lines indicative of requests for mastership of the bus by the processors. Since each local arbitrator is of common configuration with the other local arbitrators, is operating synchronously with the other arbitrators, and is provided with a similar set of inputs, each arbitrator will arrive at the same conclusion as to which processor is to become bus master. Accordingly, an external bus arbitrator is not required and acknowledge lines are not required to communicate signals indicative of the result of the bus arbitration to the processors.

Abstract: High-speed sampler methods and structures are provided to enhance the correlation between an input signal Sin and a corresponding sampler output voltage Vout. An input buffer is enabled during sampling time periods and disabled during holding time periods. In the sampling time periods, a sampling capacitor Cs is directly charged through the input buffer and the capacitor's bottom plate to a charge that corresponds to the input signal Sin. In the holding time periods, the disabled input buffer is isolated from the sampling capacitor Cs and a common-mode signal Scm is directly coupled to the capacitor's bottom plate to provide the output voltage Vout at the capacitor's top plate. Preferably, an output capacitor Co is coupled to the sampling capacitor Cs and charge from the sampling capacitor Cs is transferred to the output capacitor Co.

Abstract: A data processor is provided which has integrated therein at least two of a bootstrap memory, a program memory and a data memory, wherein the at least two memories are of the same construction. In an exemplary embodiment, the memories are flash EEPROM memories. The data memory is provided with registers for temporarily storing the contents of an entire row of memory such that modifications can be easily made to a single bit within the row by storing the contents of the row, erasing the row, modifying the data and storing the data back in the row.

Abstract: An operational amplifier having two differential input stages. A first one of the stages comprises a pair of first input transistors and another one of such stages comprises a pair of second input transistors. The second input transistors are complementary in type to the first input transistors. A comparator is fed by a sense signal and a reference signal, such sense signal being related to at least one of a non-inverting and an inverting input signal fed to the operational amplifier. The comparator produces a control signal in accordance with a difference between the sense signal and the reference signal. A switching network is responsive to the control signal and couples an output of either the first one of the stages or the second one of the stages to an output of the operational amplifier selectively in accordance with the control signal.

Abstract: First and second clocked digital sources are provided in each of two data paths, and are clocked by respective direct and complementary clock pulses. The clocked outputs of these devices are directed to a multiplexer where the inter-leaved data path signals are recombined into a single output line. This multiplexer includes clocked transmission gates, the clock signals for which are shifted in time by 90° from the clock signals applied to the originating signal sources. The result is that additional time is made available for sampling the digital signals applied to the multiplexer.