Abstract: A high permeability magnetic core structure introduces a magnetic field to an intergrated circuit during testing. The magnetic core is mounted in an automatic tester and is integrated into the mechanical test site assembly that holds the integrated circuit in place during testing. Wound wire coils, mounted on the core structure, generate the magnetic field that is used for the test.

Abstract: A dynamic bridge system with common mode range extension includes a dynamic bridge circuit having a pair of input terminals for receiving common mode and normal signals, a pair of intermediate terminals and an output terminal and reference terminal; a differential amplifier has its inputs connected to the intermediate terminals and its output connected to the output terminal; a pair of balanced loads is each connected at one end to an intermediate terminal; and an inverting amplifier responsive to the common mode signal at the inputs of the differential amplifier drives the other ends of the balanced loads in opposition to changes in the common mode signals at the inputs of the differential amplifier.

Abstract: A switching voltage regulator employs a “dual modulation” scheme to control the regulator's switching components. A control circuit indirectly monitors load current. When the load decreases, the control circuit reduces both the duty ratio and the frequency of the control signals which operate the switching transistors, thereby maintaining a high efficiency level over a wider output current range than can be achieved with fixed-frequency control signals. In a preferred embodiment, the regulator employs three operating modes. For heavy loads, the switching components are operated at a constant frequency. For moderate-to-light loads, the dual modulation control scheme is used. For light loads, the regulator enters a “pulse-skipping” mode which can achieve very low operating frequencies to further improve efficiency.

Abstract: An IC resistor and capacitor fabrication method comprises depositing a dielectric layer over existing active devices and metal interconnections on an IC substrate. In a preferred embodiment, a layer of thin film material suitable for the formation of thin film resistors is deposited next, followed by a metal layer that will form the bottom plates of metal-dielectric-metal capacitors. Next, the capacitors' dielectric layer is deposited to a desired thickness to target a particular capacitance value, followed by the deposition of another metal layer that will form the capacitors' top plates. The metal layers, the capacitor dielectric layer, and the thin film material layer are patterned and etched to form TFRs and metal-dielectric-metal capacitors as desired on the IC substrate. The method may be practiced using any of several alternative process sequences. For example, the bodies of the TFRs can be formed before the deposition of the capacitors' layers.

Abstract: A method for stabilizing thin film structures fabricated on an I.C. wafer requires the performance of a rapid thermal annealing (RTA) step after the thin film material, preferably silicon-chromium (SiCr) or silicon chromium carbide (SiCrC), is sputtered onto the wafer. The RTA step stabilizes the TF and thereby increases the film's integrity. With the TF structures stabilized, the effect of subsequent high temperature process steps on the film is reduced. The stabilization method enables TF resistors thereby formed to attain a higher degree of accuracy, and thus to improve the ability with which resistors can be matched. Resistor TCR and sheet rho consistency are also improved, both within a given wafer and from wafer to wafer.

Abstract: A buffer circuit includes a delay circuit which is interposed between a signal source and a following circuit. The delay circuit propagates a signal from an input to an output; the signal has associated desired timing relationships between its rising and falling edges. The delay circuit controls the propagation delays of the signal's rising and falling edges such that when the signal arrives at a selected downstream node, it has the desired timing relationships. The delay circuit adjusts the propagation delays in accordance with two correction signals: one which reduces errors induced by imperfections in the signal path through which the test signal propagates, and one to reduce errors due to thermal effects that arise when propagating a periodic test signal having a duty cycle other than 50% through the signal path.

Abstract: A micromachined accelerometer is hermetically sealed in a reduced oxygen environment to allow organics to survive high temperature sealing processes.

Abstract: A method for capping active areas of a semiconductor wafer uses photolithography to define areas of sealant on the cap wafer to thereby reduce the amount of space required for attaching the cap wafer to the semiconductor wafer carrying active areas to be capped. Using photolithography in this manner increases the amount of space on the semiconductor wafer that can be used to form active areas which, in turn, improves the density of active area on the semiconductor wafer. In one embodiment, the method includes the steps of applying a photoimageable layer, photoimaging the photoimageable layer to define a pattern including remaining regions of the photoimageable layer and removed regions of the photoimageable layer, and using the pattern to define the sealant regions on the semiconductor wafer.

Abstract: An improved successive approximation analogue-to-digital converter system including a D/A converter and a comparison capability, wherein a first trial value is stored in a successive approximation register and a comparison is made of relative amplitude of D/A converter output with respect to analogue signal amplitude, and an iterative process is performed in which a subsequent trial value is stored in the successive approximation register before the comparison is repeated. The improvement comprises conducting only one comparison for each trial, with the subsequent trial value for a plurality of iterations being greater than one-half the first trial value, such that a first trial value determined in error is corrected during subsequent iterations. Apparatus implementing the improved successive approximation A/D is also described.

Abstract: A dual-edge pulse-triggered flip-flop comprising a gated data latch and a gated scan latch coupled in series with the data latch. In normal operation, the data latch captures a data input D in response to clock pulses ckp generated on each edge of a system clock ck. During an input scan operation, a selected stimulation bit presented on a scan input SI is transferred first into the scan latch in response to a scan input clock ak, and then into the data latch in response to a scan output clock bk. This stimulation bit is simultaneously presented on a scan output SO. During an output scan operation, a data bit Q presented on the scan input SI is transferred first into the scan latch in response to the scan input clock ak, and then into the data latch in response to the scan output clock bk. This data bit is simultaneously presented on the scan output SO.

Abstract: A high-frequency RMS-DC converter having extended dynamic range operates by dynamically at low cost by adjusting the scaling factor (denominator) of a detector cell such as a squaring cell. The output from the squaring cell is averaged to generate a final output signal which can be fed back to a scaling input for operation in a measurement mode, or used to drive a power amplifier in a controller mode. By implementing the squaring cell as a transconductance cell using a modified multi-tanh structure, the scaling factor can be adjusted by dynamically changing the tail current through the cell which, in the measurement mode, is achieved by connecting the averaged output back to the squaring cell. An exponentially responding amplifier can be used in the feedback loop to provide a linear-in-dB output characteristic.

Abstract: A direct-digital synthesizer for generating a waveform includes a digital accumulator fed by a phase increment word and a series of clock pulses for successively adding the phase increment word to produce a series of N bit phase words. A table or trigonometric engine produces sine and cosine digital signals related to the M most significant bits of the phase word produced by the accumulator. A feedback loop is fed by truncation error words comprising at least a portion of N-M least significant bits of the N bit phase words producing truncation error compensation words. The feedback loop includes a digital filter. The feedback loop includes a digital filter. The feedback loop including the digital filter provides a low pass truncation error response to the truncation error having at least one zero in the transfer function thereof at DC.

Abstract: A circuit and method for trimming and simulating the effect of trimming a plurality of IC parameters. Trim signals which affect respective IC parameters are generated with respective digital-to-analog converters (DACs) in response to digital bit patterns. A parameter to be trimmed is selected, a bit pattern is applied to a DAC and a trim signal generated, and the value of the parameter that results is measured. Bit patterns are iteratively created until one is identified that brings the parameter within an acceptable range. The identified bit pattern is then permanently encoded using programmable subcircuits containing poly fuses. The bit patterns are received serially to conserve I/O pins. A number of DACs are provided to enable a number of different parameters to be simulated and trimmed. A switching network is provided that selectably switches otherwise inaccessible internal nodes to an I/O pin for measurement. The trimming circuitry.

Abstract: A direct conversion receiver having a homodyning section fed by a received radio frequency signal having a carrier frequency and reference signal having the carrier frequency; and a filter coupled to the monodyning section. The filter includes a plurality of serially coupled high pass filter stages. The high pass filter section acts as a DC offset correction loop that eliminates the serial effect of many amplifier sections on DC offsets arising within components, while maintaining a sufficiently low cutoff frequency to avoid adversely impacting information integrity at higher frequencies. The high pass filter sections also enable the integration of the needed capacitors, thus minimizing external components and connections. Each filter stage includes an amplifier and a low pass filter coupled in a negative feedback arrangement with the amplifier. Each low pass filter is adapted to have the cutoff frequency thereof switch from an initial high cutoff frequency to a subsequent lower cutoff frequency.

Abstract: A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file. The register file may further include at least one control information register for storing control information used by the bit transfer mechanism.

Abstract: A data bus system with data integrity verification is arranged so that a bus device receiving a message always responds by sending a check sequence back to the message originating device; i.e., a check sequence is automatically returned to a message originating device as part of every bus transaction. The originating device reads the returned check sequence and uses it to verify the integrity of the data transferred between the two devices. The check sequence can be created by the receiving device based on the data conveyed, or the receiving device can simply echo back a check sequence that is appended to the incoming data.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: Feedback control systems and methods are provided for correcting residue signal offset errors in subranging ADCs. The systems and methods eliminate clock-to-clock offset changes and reduce noise generation. An exemplary control system includes a feedback loop around a residue sampler and a residue amplifier that includes a) a feedback sampler that resamples the output signal of the residue sampler to produce a resampled residue signal, and b) an offset current generator that delivers an offset current to the residue amplifier with a current magnitude that is responsive to the resampled residue signal. The sampling of the residue and feedback samplers is time shifted to block the propagation of spurious signals that are typically generated in DACs of the subranging structure.

Abstract: A method and circuit for providing a reference voltage to a charge balance circuit. The method includes transferring charge corresponding to VBE and charge corresponding to &Dgr;VBE to a summing node of the charge balance circuit, where VBE is a voltage produced across a p-n junction and where &Dgr;VBE is a difference between two VBE voltages. With such method, instead of forming a bandgap reference circuit which produces a bandgap reference voltage and applying such voltage to the reference sampling and charge transfer circuit, charge corresponding to VBE and charge corresponding to &Dgr;VBE are transferred to the input summing node of the modulator in correct proportion and with a polarity corresponding to the modulator output.

Abstract: A differential switch accepts a binary control signal and its complement (which may be skewed with respect to the control signal) and latches both signals simultaneously. The latched output signals drive the control terminals of a differential switch pair which connects one of two terminals to a third terminal, depending upon the state of the control terminals. The differential switch may optionally include an inverter which complements the binary control signal, thus eliminating the need for external inversion of the control signal. The switch is particularly applicable for use in a digital to analog converter.