Patents Assigned to Analog Devices
  • Patent number: 6232815
    Abstract: A complementary waveform driver is disclosed that generates output signals SOUT with arbitrary high and low drive states with respect to an independently controlled baseline signal SBL. Accordingly, the driver can generate very fast and flexible waveforms with multiple levels and baseline components. The driver implements complementary differential pairs of transistors that alternately source and sink programmable currents to an output port, creating an output waveform with excellent rising and falling edge symmetry, and greatly improved fidelity, especially at low level voltage swings. A complementary amplifier stage defines the baseline voltage level. When combined with a programmable active load and window comparator, the driver is particularly suited for pin electronics in automatic test equipment (ATE) applications.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: May 15, 2001
    Assignee: Analog Devices, Inc.
    Inventor: Anthony E. Turvey
  • Patent number: 6229292
    Abstract: A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved with a technique referred to as “optimal voltage positioning”, which keeps the output voltage within the specified boundaries while employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed. The invention can be used with regulators subject to design requirements that specify a minimum time Tmin between load transients, and with those for which no Tmin is specified.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: May 8, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Richard Redl, Brian P. Erisman, Jonathan M. Audy, Gabor Reizik
  • Patent number: 6225857
    Abstract: A non-inverting driver circuit for an LDO pass device employs a level-shifting inverter stage followed by a normalizing inverter stage. The level-shifting stage converts the output common-referenced output of the error amplifier to a current, which is provided to the normalizing inverter. The normalizing stage is referred to the LDO input voltage, enabling its output signal to remain largely invariant with respect to changes in input voltage. The driver is preferably configured to have a low output impedance, so that when driving the high gate capacitance of a MOS pass device, the resulting pole is moved to a higher frequency than would be possible with a non-inverting driver having a high output impedance. With the driver being non-inverting and the low frequency pole moved higher, frequency compensating the regulator is simplified.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: May 1, 2001
    Assignee: Analog Devices, Inc.
    Inventor: A. Paul Brokaw
  • Patent number: 6223598
    Abstract: A suspension mounting arrangement for a suspended layer in a semiconductor accelerometer, the layer being suspended above and spaced apart from a substrate. The arrangement includes a common anchor point associated with the substrate; first and second anchor points associated with the suspended layer; a first flexible serpentine arm coupled between the first anchor point and the common anchor point; and a second flexible serpentine arm coupled between the second anchor point and the common anchor point. The first and second flexible serpentine arms are symmetrically configured with respect to one another.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: May 1, 2001
    Assignee: Analog Devices, Inc.
    Inventor: Michael W. Judy
  • Patent number: 6225683
    Abstract: A “paddle-under-lead” (PUL) leadframe has the inner portions of an I.C. package's leads extend along the top of a paddle, to which they are affixed. An I.C. die is affixed to the top of the inner leads to form an I.C. package. Because the die is affixed directly to the leads, heat generated by the die is conducted out of the package via the package's leads, with the paddle serving as a heat spreader and heat sink. The leadframe's inner leads are affixed to the paddle, rather than separated from it as is done conventionally; this enables a larger die size to be accommodated within the same standard package size. A bifurcated inner lead design, usable with the PUL leadframe and others, divides the inner portions of an I.C. package's leads into laterally offset upper and lower sections, with the upper section serving as a wedge bond shelf and the lower section downset from the upper section.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: May 1, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Prasad V. V. Yalamanchili, Oliver J. Kierse
  • Patent number: 6222889
    Abstract: A trellis decoding system is provided having a memory for storing a sequence of received signals. The signals have been encoded prior to transmission by a trellis encoder such that each of a predetermined plurality of symbols represents an allowed transition from an originating state to a predetermined limited number of terminating states. The system includes a trellis decoder for decoding the sequence of received signals into a corresponding sequence of the symbols. A soft decision generator is provided. The soft decision generator is responsive to the signals stored in the memory and to the output of the trellis decoder and determines a soft decision parameter representative of confidence level of the trellis decoder in properly decoding the received signal into each one of the symbols. The determined soft decision parameter is tagged to each one of such symbols subsequent to the trellis decoder decoding the sequence of received signals into the corresponding sequence of symbols.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: April 24, 2001
    Assignee: Analog Devices, Inc.
    Inventor: Kwan Yee Lee
  • Patent number: 6208174
    Abstract: Comparator systems and methods are provided that isolate their input and output processes from each other. Comparator signals are converted to a differential current in an input process and are carried via the differential current to an output process which converts the differential current to a comparator output signal. Supply rails that are coupled to the input process are isolated from the output process and supply rails that are coupled to the output process are isolated from the input process. The differential-current transmission and supply rail isolation effectively reduce feedback and, in addition, the differential current enhances common-mode signal rejection.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: March 27, 2001
    Assignee: Analog Devices, Inc.
    Inventor: Michael Clarence Hopkins
  • Patent number: 6204719
    Abstract: An RMS-to-DC converter implements the difference-of-squares function by utilizing two identical squaring cells operating in opposition to generate two signals. An error amplifier nulls the difference between the signals. When used in a measurement mode, one of the squaring cells receives the signal to be measured, and the output of the error amplifier, which provides a measure of the RMS value of the input signal, is connected to the input of the second squaring cell, thereby closing the feedback loop around the second squaring cell. When used in a control mode, a set-point signal is applied to the second squaring cell, and the output of the error amplifier is used to control a variable-gain device such as a power amplifier which provides the input to the first squaring cell, thereby closing the feedback loop around the first squaring cell.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: March 20, 2001
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 6204654
    Abstract: A dynamically boosted current source circuit improves the response speed of a circuit responsive to a transitioning input signal. The circuit's responsiveness varies with the magnitude of the current provided to an identified node, and a current source capable of providing nominal and boosted currents is connected to the node. A threshold detector detects the occurrence of an input signal transition prior to its detection by the responsive circuit, and triggers the current source to provide the boosted current; this improves the responsive circuit's speed by charging or discharging identified node capacitances which hinder its operation. The identified node can be an input node, an output node, or an internal node. The current source provides the boosted current for a predetermined time interval, or until the input signal crosses a second threshold, enabling response speed to be increased without a significant increase in supply current.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: March 20, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Evaldo M. Miranda, Jonathan M. Audy, David Thomson
  • Patent number: 6198330
    Abstract: Inverters are provided which adapt their output impedance to the driven load and thereby enhance inverter performance (e.g., current drive, switching speed and common-mode rejection). An inverter embodiment includes a complementary common-source stage arranged to drive an output port in response to signals at a first side of a differential input port and a complementary common-drain stage arranged to drive the output port in response to signals at a second side of the differential input port.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: March 6, 2001
    Assignee: Analog Devices, Inc.
    Inventor: Michael Clarence Hopkins
  • Patent number: 6194886
    Abstract: An Early voltage and beta current compensated cascode current mirror includes a cascode current mirror having an input stage responsive to an input current, a current mirror circuit having a first stage responsive to the input stage and a second stage responsive to the first stage, and an output stage responsive to the second stage for providing an output voltage and current; and a compensation circuit, responsive to the cascode current mirror, having a first compensation stage, a second compensation stage and a bootstrapping buffer, the first compensation stage, in response to a change in the output voltage, impressing a corresponding change in voltage on the second compensation stage, the second compensation stage thereby providing a change in current to the cascode current mirror for cancelling current errors induced by base current modulation in the output stage, the bootstrapping buffer, in response to the change in voltage, impressing a corresponding change in voltage on the first compensation stage to
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: February 27, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Stefano I. D'Aquino, Adrian P. Brokaw, Kimo Y. F. Tam, David H. Whitney
  • Patent number: 6194962
    Abstract: A system for adaptively trimming the input offset voltage of an op amp employing an input stage with complementary differential pairs provides accurate VDos trimming over the amplifier's entire common-mode input range, by providing an “adaptive” trim signal that varies with the current conducted by one of the complementary pairs. Switching circuitry insures that only one differential pair is active at a time, except in a transition region in which both pairs are partially conducting. The use of an adaptive trim signal enables Vos to be kept low over the full range of common-mode input voltages, including in the amplifier's transition region.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: February 27, 2001
    Assignee: Analog Devices, Inc.
    Inventor: Marcellus R. Chen
  • Patent number: 6192757
    Abstract: A monolithic capacitance-type microstructure includes a semiconductor substrate, a plurality of posts extending from the surface of the substrate, a bridge suspended from the posts, and an electrically-conductive, substantially stationary element anchored to the substrate. The bridge includes an element that is laterally movable with respect to the surface of the substrate. The substantially stationary element is positioned relative to the laterally movable element such that the laterally movable element and the substantially stationary element form a capacitor. Circuitry is disposed on the substrate and operationally coupled to the movable element and the substantially stationary element for processing a signal based on a relative positioning of the movable element and the substantially stationary element. A method for fabricating the microstructure and the circuitry is disclosed.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: February 27, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Robert W. K. Tsang, Theresa A. Core, Steven J. Sherman, A. Paul Brokaw
  • Patent number: 6194958
    Abstract: A filter having a semiconductor chip and a low pass filter section on the chip. The low pass filter section includes a filter transconductor and a filter capacitor connected to the filter capacitor. The low pass filter section has a cut-off frequency related to the transconductance, gmF, of the filter transconductor and the capacitance of the filter capacitor. A gm control circuit having a control circuit transconductor is provided. The gm control circuit includes a first oscillator for producing a reference frequency. The first oscillator has a portion thereof on the chip and an off-chip capacitor and off-chip resistor. The reference frequency is a function of the capacitance of the off-chip capacitor and the resistance of the off-chip resistor. A second oscillator is on the chip and produces a variable frequency. The second oscillator has an on-chip capacitor.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: February 27, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Marc E. Goldfarb, Wyn T. Palmer
  • Patent number: 6191619
    Abstract: High-speed signal translators are provided to convert differential input signals (e.g., ECL signals) to single-ended output signals (e.g., CMOS signals). An exemplary translator is formed with first and second current mirrors, first and second complimentary differential pairs of transistors, a complimentary transistor output stage and first and second current-diverting transistors. The complimentary output stage initially generates the single-ended output signal in response to currents received from the complimentary differential pairs. When the output signal has been established, the current-diverting transistors respond by carrying at least portions of the currents supplied by the complimentary differential pairs. The current-diverting transistors also drive the current mirrors to divert other portions of these currents away from the complimentary output stage. Stored charges in the output stage are accordingly reduced and its response time enhanced.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: February 20, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Carl W. Moreland, Michael R. Elliott
  • Patent number: 6188189
    Abstract: A fan speed control system for an electronic equipment enclosure comprises means for determining temperature at a plurality of locations within the enclosure, means for determining operating parameters for the fan control system, means for setting operating speed of at least one cooling fan, and means for exchanging information signals relating to fan speed control system operation with an external controller. A method is also provided for controlling fan speed for an electronic equipment enclosure comprising the steps of determining temperature at a plurality of locations within the enclosure, determining operating parameters for the fan control system, setting operating speed of at least one cooling fan, and exchanging information signals relating to fan speed control system operation with an external controller.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: February 13, 2001
    Assignee: Analog Devices, Inc.
    Inventor: John Blake
  • Patent number: 6181118
    Abstract: A control circuit (1) for controlling a FET (2) for outputting a 3.3 volt or a regulated 1.5 volt output to an AGP bus on a PC motherboard in response to a TYPEDET signal being applied to a control terminal (3) of the control circuit (1) through an input (6) of a voltage divider circuit (8). The TYPEDET signal is received from a video card receiving slot and indicates the type of video card in the slot of the motherboard. An amplifier (20) outputs a control signal to the gate of the FET (2) for either disabling the FET (2), or enabling the FET (2) to output the 1.5 volt or the 3.3 volt outputs. A decoding circuit (30) decodes the state of the control terminal (3) and controls the amplifier (20) to disable the FET (2) during power up. When the TYPEDET signal of zero volts, the FET (2) is operated to output the 1.5 regulated voltage output. When the TYPEDET signal is floating, the FET (2) outputs the 3.3 source voltage.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: January 30, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Patrick Meehan, Brian Anthony Moane, George Francis Clernon
  • Patent number: 6172549
    Abstract: An RMS-to-DC converter implements the difference of squares function using two squaring cells operating in opposition to attain a balance. Each of the squaring cells is implemented as a grounded-base transistor and a two-transistor current mirror. The emitter of the grounded-base transistor is coupled to the input terminal of the current mirror at a node which receives the input signal. The collector of the grounded-base transistor and the output of current mirror are coupled together to generate an output current having a square-law relationship to the input signal. One of the squaring cells receives the input signal and operates at high frequencies (HF), while the other receives a feedback signal and operates in a quasi-DC mode. In a measurement node, a nulling circuit closes a feedback loop around the DC squaring cell to null the output currents from the squaring cells.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: January 9, 2001
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 6172636
    Abstract: Structures and methods are provided that linearize and stabilize the gain of adjustable-gain folding amplifiers. Accordingly, these folding amplifiers are suited for use in various compound ADCs where they improve the performance of subsequent folding amplifier stages, increase the number of allowed subsequent stages and replace the functions of other portions of compound ADCs (e.g., subranging ADCs).
    Type: Grant
    Filed: July 13, 1999
    Date of Patent: January 9, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Frank Murden, Michael R. Elliott
  • Patent number: 6172551
    Abstract: Current switches are arranged to reduce signal transit-time variations when they switch current signals that have a wide range of current magnitudes. The transit-time variations are reduced by shifting the range of currents that are carried by switching transistors. In particular, a current range is shifted upward to a higher current range in which the variation of the transistors' transition frequency fT is reduced. In general, the switches include a differential pair of transistors, an offset current source that generates an offset current and a current-steering system that steers the offset current along a current path that includes a switched-on transistor but excludes the output port of that transistor.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: January 9, 2001
    Assignee: Analog Devices, Inc.
    Inventor: Edward Barry Hilton