Abstract: A transconductance filter control system for compensating for drift in transconductance of a slave transconductance amplifier in a continuous time transconductance filter including: a master transconductance amplifier having an output which is a function of its transconductance and a control input for controlling the transconductance of the master transconductance amplifier; a tuning signal source for providing a tuning signal representative of a preselected characteristic of the transconductance filter; a comparing circuit, responsive to any deviation from a predetermined difference between the tuning signal and the output of the master transconductance amplifier, representative of a deviation of the transconductance of the master transconductance amplifier, for providing a compensation signal; and a circuit for applying the compensation signal to the control input of the master transconductance amplifier and to the control input of the slave transconductance amplifier in the transconductance filter to adjus

Abstract: CMOS comparators are provided that have substantially improved operating frequency ranges. They include first and second differential pairs of transistors and first, second, third and fourth current mirrors. The first and second differential pairs both respond to an analog input signal but only the first differential pair is coupled to define an output port. The first and second current mirrors are cross coupled to the transistors of the first differential pair but each of the third and fourth current mirrors are cross coupled between a respective transistor of the second differential pair and a respective transistor of the first differential pair. The third and fourth current mirrors provide high-speed discharge paths for parasitic circuit capacitances. The comparator structure can be adjusted to control comparator slew rates and hysteresis.

Abstract: An IC monitoring chip (10) for remotely monitoring the output of a thermal diode (5) formed in the substrate of a CPU (2) for monitoring the temperature of a thermal plate (3) of the CPU (2) comprises a signal conditioning circuit (12) which relays the output from the diode (5) to an analog-to-digital converter (14), which in turns outputs a two's compliment signal to an adder (22). The adder (22) adds the two's compliment signal to a temperature offset value stored in a temperature offset register (17), which compensates for the temperature difference between the diode (5) and the thermal plate (3). Comparators (24) and (25) compare the output from the adder (22) with upper and lower predetermined temperature limits in upper and lower limit registers (19) and (20) for determining the temperature of the thermal plate (3). The temperature offset value is stored in ROM (35) of the computer (1) and is written to the register (17) each time the computer (1) is powered up.

Abstract: Spatially offset, row interpolated image sensor includes a linear array sensor having a first row of longitudinally extending pixels with a first spatial periodicity and a second row of longitudinally extending pixels having a second spatial periodicity laterally adjacent the first row and longitudinally staggered with respect to the first row; and a read circuit for individually, selectively sampling pixels of the rows for producing a composite output which has a combined spatial periodicity which is shorter than either of the first and second spatial periodicities and has a number of samples equal to the combined samples of both the rows.

Abstract: Waveform synthesizers are disclosed that generate an output signal S.sub.OUT with independent response to a common-mode input signal S.sub.CM, an input data signal S.sub.D and a current programming signal S.sub.PRGM. The synthesizers include a differential pair of first and second transistors that respectively respond to the input data signal S.sub.D and to a fixed reference signal V.sub.REF. Because the second transistor is referenced to a fixed potential, current-pumping action of parasitic capacitances is reduced with consequent reduction of transient signals in the output signal S.sub.OUT. Signal transients are further reduced with diodes that are arranged to block transient-current interchange between the first and second transistors.

Abstract: A stress relief substrate having a pair of ball grid arrays (BGAs) is interposed between a PC board and an electrical component. The BGAs are electrically connected through vias in the stress relief substrate to connect component circuitry to the PC board. In one embodiment, the BGAs are offset on a flexible substrate so that there is some open space between the edges of electrically connected solder balls. This allows the substrate to warp during thermal cycling and absorb the stress caused by TCE mismatch. In another embodiment, the BGAs are aligned on a rigid substrate that is formed with holes interposed between the solder balls. This reduces the amount of material that interconnects the solder balls so that the substrate tends to flex rather than transfer the TCE stress to the solder balls.

Abstract: A broadband modem hybrid transformer couples a broadband modem to a plain-old-telephone (POTs) line. The hybrid includes a full bridge having an impedance matching network to reduce the transhybrid attenuation of the hybrid. The second matching network(s) include various resistive and reactive components which together provide an impedance value selected based upon the impedance of the telephone line typically reflected into the primary windings of the transformer. The matching network increases the transhybrid attenuation of the hybrid, and thus reducing the amount of noise which couples from the modem transmit circuit to the modem receive circuit through the hybrid.

Abstract: Linearized unity-gain folding amplifiers include first and second differential pairs of transistors that have offset voltages between control terminals and first current terminals. The control terminals are differentially coupled through input paths to a differential input port and the joined first current terminals receive respective first and second currents through respective first and second level-shift resistors. Thus, folded and level-shifted signals can be differentially coupled via output paths between the first and second level-shift resistors and an output port. For each of the differential pairs, at least one correction voltage is generated to substantially match the offset voltage of one of the transistors of that differential pair when a differential input voltage has one polarity and the offset voltage of another of the transistors when the differential input voltage has a different polarity.

Abstract: The current flow from a temperature-variable current source to a Hall-effect element is adjusted according to sensed temperature conditions of the element to compensate for temperature-dependent changes in the magnetic-field sensitivity of the Hall-effect element and in the magnitude of the permanent magnetic fields of magnetic components sensed by the element. A trimmable resistor is connected between two external terminals of a Monolithically integrated circuit to provide external control over the sensitivity of the temperature variable current source to changing temperature conditions. The device also alternately switches the quadrature states of output and bias supply contacts of the Hall-effect element to compensate for the offset and drift thereof.

Abstract: A device for detecting with differential capacitors accelerations in more than one orientation through time-division multiplexing. A micromachined mass is movable along or about any axis in response to a force. The mass forms the common electrode of a set of differential capacitors, wherein the other electrodes of each differential capacitor are fixed. With each differential capacitor, one fixed electrode is set to one voltage and the other fixed electrode is set to a second voltage. The mass is connected to the input of an amplifier and to a switch for connecting the mass to a fixed voltage. The output of the amplifier is coupled to a demodulator for each orientation. A timing circuit activates one demodulator at a time. By toggling the voltages on the fixed electrodes of the differential capacitor corresponding to the active demodulator, the movement of the mass in the orientation corresponding to the active demodulator can be determined.

Abstract: A write channel in read/write disc drive system for writing data signals to a drive includes a variable delay circuit having a number of selectable taps for correcting for non-linear transition shift; and a delay locked loop circuit responsive to the data signal for controlling the delay of the variable circuit.

Abstract: An integrated circuit comprises means responsive to a normally changing signal at an input of the integrated circuit to implement a primary function of the circuit, and means for monitoring this normally changing signal at the input in question of the integrated circuit. This monitoring means is responsive to suspension of the normally changing signal to communicate a signal for implementation of a secondary function of the circuit. In an exemplary embodiment, the invention is directed towards implementation of power-down of the circuit, without using an explicit power-down or reset pin. An input signal which normally changes at minimum rate, e.g. preferably a clock signal, is held in a fixed state for a minimum duration to invoke the reset or power-down mode. An integrated circuit may thus be powered-down or reset where no explicit power-down or reset pin is available.

Abstract: A programmable pulse slimmer system for a low pass ladder filter includes a filter input current source for providing to a low pass ladder filter the input signal to be filtered; and a high frequency boost current source for injecting into the low pass ladder filter forward of the first inductor device a high frequency load current which is a scaled inverse replica of the input signal to provide gain at the high frequency end of the low pass band of the low pass ladder filter.

Abstract: A progressive-compression logarithmic amplifier, amplifier stage, and method for increasing the bandwidth of a differential-input progressive-compression logarithmic amplifier are disclosed. The amplifier stage provides positive gain increases for decreases in the impedance of the load driven by the stage. When multiple amplifier stages of this type are cascaded, the gain increase in each stage compensates for high-frequency roll-off due to the input capacitance of the following stage. The compensating is activated by the roll-off effect itself, making the device self-compensating. This is preferably accomplished by providing a drive current sensing path that makes each node of the stage's differential output respond in opposition to the drive current drawn at the stage's other differential output--that is, an increase in drive current at one output node drops the voltage at the other output node.

Abstract: A digital television (DTV) receiver receives a data signal that is divided into a plurality of segments each separated by a known data segment sync sequence. The receiver includes a data segment sync signal detector that receives the data signal and filters the signal to provide a filtered data signal. The detector computes the difference between samples of the filtered data signal and an average expected filtered signal value that is representative of a nominal filtered signal value in the middle of the segment sync sequence. The detector then computes the absolute value of the computed difference, and the resultant absolute value is summed with a sampled value from the previous segment and the summed value is stored into an accumulator. The process is repeated for several segments. The location of the data segment sync sequence within the segment is determined by comparing the summed values to determine the smallest summed value, which represents the center of the segment sync sequence.

Abstract: An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise.

Abstract: A tri-state input detection circuit produces two binary outputs that indicate whether a tri-state input signal is high, low, or in a hi-impedance state. A pair of transistors conduct a current in response to a tri-state signal presented at an input node. Circuitry is provided to pull the input node to a known voltage when the input signal is in its hi-Z state. The transistors are series-connected to respective current sources, with the junctions between the transistors and their current sources forming the circuit's binary outputs. The output impedances of the current sources are made less than those of their respective transistors, so that when turned on by the input signal, a transistor pulls its associated output high or low. The circuit produces a unique binary output for each of the three input signal states.

Abstract: The chopping frequency driving a chopper-stabilized amplifier (CSA) is dynamically varied between an upper and lower frequency limit to reduce the intermodulation distortion, clock noise and low-frequency noise found in prior art designs. The upper limit is set to accommodate the settling times required by the CSA's memory capacitors, and the lower limit is set to a non-zero frequency significantly greater than DC to reduce low frequency noise. The two limits permit IMD and clock noise to be widely scattered and enable a near optimum trade off between IMD and chopping noise on one hand, and low frequency noise on the other. The chopping frequency is preferably generated digitally with a loadable counter which divides down a fixed frequency master clock, with the binary value presented at the counter's load inputs periodically varied to dynamically vary the division ratio and thus frequency modulate the chopping frequency.

Abstract: Time-delay circuits are realized with first and second capacitors, a differential amplifier, a programmable current source and a differential pair of transistors. The current source directs first and second currents to the first and second capacitors and the differential pair steers a third current of the current source to either selected one of the capacitors to provide charging and discharging currents to the capacitors. The differential amplifier generates a delayed output pulse in response to voltages of the first and second capacitors. The capacitors are preferably formed by the interconnection system of an integrated circuit, i.e., the metallic circuit paths that are typically carried on an integrated-circuit substrate. N+1 of the delay circuits are combined with a phase comparator to form an interpolator that responds to an input data pulse by generating N output data pulses that span a period between the input data pulse and a successive input data pulse.

Abstract: Improved data scramblers and swapper cells and improved digital to analog converters are provided. The improved swapper cells permit data to be propagated through the cell immediately upon receipt. The determination of whether to swap data or pass it directly through is based on a history of data values propagated through the cell, but is independent of the values of the particular inputs being swapped. The data scrambler is structured to permit the possible data inputs on swapper cells in the scrambler to be restricted. A minimum delay data scrambler for use in a fast digital to analog converter is disclosed using these components.