Abstract: A method and system for high bandwidth, high gain offset compensation in a read channel integrated circuit includes zeroing the analog read signal applied to the signal path at a first location in the read channel integrated circuit path prior to a first amplifier which has a first gain and a first bandwidth magnitude characteristic with a high frequency boost; coupling a signal from the first amplifier to a second amplifier which has a second gain larger than the first and a second bandwidth magnitude characteristic having high frequency roll-off; and further coupling the signal further from the second amplifier to a storage device and feeding back the signal stored in the storage device to the first amplifier to apply the high frequency boost of the first bandwidth magnitude characteristic to compensate for the high frequency roll-off of the second bandwidth magnitude characteristic; decoupling the signal from the storage device and removing the zeroing of the analog read signal applied to the signal path.

Abstract: A cubic-type function generator combines the outputs from three differential pairs of transistors to generate an output current that varies in a cubic-type manner in response to the input voltage. The input offset voltages of the three differential pairs are set to different values so that the center of the hyperbolic tangent function for each differential pair is shifted along the input axis. By combining the outputs from the three differential pairs out of phase, the separate tanh functions combine to form an output function having an S-shaped curve. The amplitude of the output curve can be adjusted by varying the absolute magnitude of the bias currents to the differential pairs. The tilt and output offset can be adjusted by varying the relative magnitude of the bias currents. By driving the differential pairs with a differential voltage signal that varies as a function of temperature, the present invention generates a cubic-type temperature function.

Abstract: A high transconductance voltage reference cell produces a large change in output current for a very small change in input voltage near a settable equilibrium point, which can be made equal to two bandgap voltages, or to non-integer multiples of the bandgap voltage without the use of a resistive divider. A first and second pair of bipolar transistors, at least one of which have unequal emitter areas, are arranged in a crossed-quad configuration, with a first resistor interposed between one of the first pair and second pair transistors and a second resistor interposed between one of the second pairs' emitters and a common point. For input voltages below the equilibrium point, most of the current through the cell flows down one side of the quad. The voltage drop across the first resistor increases with input voltage, and causes the cell current to be abruptly switched from one side of the quad to the other at the equilibrium point.

Abstract: A high performance digital signal processor includes a bidirectional communication port for communication with an external device. The bidirectional communication port includes a first transmitting circuit for transmitting to the external device a first clock on a first control line in a transmit mode and for transmitting data words on plural data lines in synchronism with the first clock, and a first receiving circuit for receiving a first acknowledge signal on a second control line in the transmit mode. The communication port further includes a second receiving circuit for receiving a second clock on the second control line in a receive mode and for receiving data words on the data lines in synchronism with the second clock, and a second transmitting circuit for transmitting a second acknowledge signal on the first control line in the receive mode. The communication port further includes switching means for switching between the transmit mode and the receive mode.

Abstract: A crystal oscillator drive circuit controls the maximum amplitude of the drive signal to a crystal by limiting the bias current of a gm cell which senses the oscillation amplitude of the crystal. The bias current is commutated by the gm cell responsive to the crystal oscillation. The commuted current is converted to a single-ended current by a current mirror. An output stage converts the current to an output voltage having a voltage swing that is determined by the resistance of a load resistor. The output voltage is then fed back to drive the crystal through a positive feedback path. The output voltage swing and the drive signal to the crystal are limited by the bias current of the gm cell. A fully complementary implementation of the drive circuit includes two complementary gm cells, two current mirrors, and an output stage having two load resistors.

Abstract: A two-stage switched-capacitor CMOS Miller-compensated amplifier uses only n-channel transistors in its signal path to reduce the deleterious effects of parasitic capacitances in the signal path while still obtaining a high transconductance in both stages. A transistor inserted in series with the Miller capacitor between the output and input of the second stage of the amplifier introduces a feedforward zero in the left half of the S-plane of the circuit. By appropriately sizing the aspect ratio and properly biasing this transistor, the second pole of the amplifier is canceled with the introduced zero. Dummy transistors having their sources and drains connected (to serve as capacitors) are cross-connected between opposite polarity inputs and outputs of a differential pair of input transistors in the first stage to effectively cancel the gate-to-drain Miller-multiplied capacitance of the input transistors.

Abstract: A video compression circuit comprises an input that receives an input video signal. A memory buffer, coupled to the input, temporarily stores a portion of the input video signal. A single horizontal filter bank, coupled to the memory buffer, high-pass and low-pass filters horizontal components of the input video signal. A single vertical filter bank, also coupled to the memory buffer, high-pass and low-pass filters vertical components of the input video signal. A recursion buffer, coupled to the filter banks, temporarily stores filter components of the input video signal for recursive filtering.

Abstract: A video clamping apparatus is described which uses transistors manufactured in a CMOS process to clamp an input video signal to a reference level during a SYNC period. A closed-loop system is provided which includes a buffer amplifier, a sample-and-hold device, a summer, a low-pass filter and a clamping circuit. The summer compares the output of the sample-and-hold device to a reference voltage which causes an output of an analog-to-digital converter to be the digital word zero.In order to maintain a high enough bandwidth of the closed loop system, a first current source is operatively coupled to the transistors of the clamping circuit during the SYNC period. When the SYNC period has ended, the first current source is decoupled from the transistors of the clamping circuit. The transconductance of the loop is, therefore, high when needed during the SYNC period.

Abstract: A magnetic sensor has a first sensing element and a second sensing element surrounding the first sensing element so that the sensor is directionally independent in a plane perpendicular to a sensing axis. The sensor can be mounted in a housing that has an end with a threaded rod or a pin for connection to a support member.

Abstract: A digital filtering system is fed by input signal and produces an output signal from either a relatively low bandwidth filter or a relatively wide bandwidth filter selectively in accordance with the time rate of change in the input signal. The output signal is produced by the relatively low bandwidth filter when the input signal is slowly varying and the output signal is produced by the relatively wide bandwidth filter when the input signal changes rapidly, after which the output is produced from the relatively low bandwidth filter when the input signal reverts to its more slowly varying characteristics.

Abstract: An ADC system includes a sigma-delta modulator that receives an analog input and provides a first digital output and an analog output. An ADC, coupled to the sigma-delta modulator, receives the analog output as an input and provides a second digital output. A digital processor, coupled to the sigma-delta modulator and the ADC, receives the first and second digital outputs and provides a digital representation of the analog input.

Abstract: A switched current temperature sensor circuit with compounded .DELTA.V.sub.BE includes an amplifier having an inverting input with a corresponding non-inverting output, and a non-inverting input with a corresponding inverting output; a first PN junction connected to the non-inverting input through a first input capacitor and a second PN junction connected to the inverting input through a second input capacitor; a current supply including a low current source and a high current source; a switching device for applying in the auto zero mode the high current source to a first terminal of the first PN junction and the low current source to a first terminal of the second PN junction for providing the V.sub.BE1 of the first junction to the first capacitor and for providing the V.sub.

Abstract: A forward error correction (FEC) system and method for use in a multipoint-to-point frame based synchronized transmission communication system in which data from users are sent in selected portions of data frames having coded symbols added thereto by encoders associated with each user. The number of bits per user assigned portions of data frames is established as an integer number of FEC code symbols. The interleaving depth is set equal to a multiple of the total number of code symbols sent by a user in a data frame. The encoders are synchronized such that all of the encoders start processing associated interleaving frames at the same time. In exemplary embodiments, the communication systems include DWMT and TDM communication systems.

Abstract: A low voltage CTAT current source includes a bipolar transistor connected across two series-connected resistors. A voltage developed across the resistors turns on the transistor, making the current through the resistors CTAT. A second transistor supplies the resistor current; its base (if bipolar) is connected to the node between the resistors, which are selected to limit the transistor's base-collector forward bias and collector-emitter voltage to a preselected fraction of the first transistor's V.sub.be, allowing the CTAT current source to operate with supply voltages of less than two junction voltage drops. A PTAT current can be combined with the CTAT current to create a temperature-compensated current. A low voltage current mirror has the respective bases of a pair of cascoded transistors connected across a resistor which is also connected between the bottom transistor's collector and a programming current.

Abstract: A segmentation circuit includes a digital noise shaper responsive to a stream of digital input words for producing a stream of first digital subwords, and a subtractor for subtracting each of the first digital subwords from a corresponding one of the digital input words to produce a stream of second digital subwords that are noise-shaped. The first and second digital subwords have smaller word lengths than the digital input words. The sum of each of the first and second subwords is equal to the corresponding digital input word. When the digital input words are noise-shaped, the first and second digital subwords are both noise-shaped. The segmentation circuit may be used in a noise-shaping digital-to-analog converter having a multi-bit loop quantizer.

Abstract: A JFET pair having unequal pinchoff voltages is operated in saturation with equal source-drain current to channel width-to-length ratios to provide a reference voltage output. Positive or negative voltage references can be implemented using either n-channel or p-channel JFETs. The pinchoff voltage difference results from the channel for one JFET having a heavier doping level than that of the other JFET.

Abstract: An accurate, low voltage, low parts-count current sense amplifier can be employed to sense either high side or low side currents. A pair of transistors are connected in a common-base configuration and biased with equal currents, with a sense resistor connected between their respective emitter circuits. A sensed current develops a voltage across the sense resistor which unbalances the transistor currents. A third transistor is connected to provide a feedback current to detect and correct the current imbalance; the feedback current is directly proportional to the sensed current, and serves as the current sense amplifier's output. The current sense amplifier requires only three transistors, can be realized with bipolar or FET devices of either polarity, and can operate at supply voltages as low as about 1.1 volts.

Abstract: A digital to analog converter having a pair of resistor strings. A first one of the resistor strings is adapted for coupling across a voltage supply. Resistors in the first resistor string produce voltages in response to current fed thereto from the voltage supply. A first switching network couples a voltage produced across a selected one of resistors in the first string across the second resistor string. The resistors in the second resistor string produce voltages in response to current passing from the first resistor string to the second resistor string through the first switching network. That is, the second resistor string is unbuffered from the first resistor string. A second switching network couples a selected one of the voltages produced at a selected one of the resistors in the second resistor string to an output.

Abstract: A high swing interface output stage integrated circuit for interfacing a data communications device with a data bus which may operate at voltage ranges outside the supply voltage of the interface circuit. An output terminal of the integrated circuit is coupled to a positive supply rail of the circuit through a substrate NPN transistor, and to a ground rail through first and second NMOS FETS. A third MOS FET also formed is coupled between the common connection of the first and second NMOS FETS and the gate of the second NMOS FET for holding the second NMOS FET off in the event of the voltage on the output terminal being driven below the ground voltage of the circuit. Other NMOS and PMOS FETS in the circuit control the operation of the circuit for determining the high and low states of the voltage on the output terminal.

Abstract: A method and apparatus for analog to digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that errors produced by nonuniform sampling are frequency-shaped to a region (i.e., shifted to higher frequencies) where they can be removed by conventional filtering techniques. In one embodiment, digital data is interpolated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter and then decimated by a fixed ratio. In another embodiment, the digital data is interpolated by a fixed ratio and then decimated under control of a sigma-delta modulated frequency selection signal that represents, on average, the data rate of the digital data to be output by the converter. The frequency selection signal is modulated using an n-th order m-bit sigma-delta modulator.