Patents Assigned to Analog Devices
  • Patent number: 6122961
    Abstract: A micromachined gyroscope has first and second coplanar bodies suspended over a substrate and movable in their plane relative to the substrate. The first body is dithered along a dither axis and is movable relative to the second body on the dither axis, but is rigidly connected for movement along an axis transverse to the dither axis. The second body is anchored so that it is substantially inhibited from moving along the dither axis, but can move with the first body along the transverse axis. The gyro has stop members and an anti-levitation system for preventing failure.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: September 26, 2000
    Assignee: Analog Devices, Inc.
    Inventors: John A. Geen, Donald W. Carow
  • Patent number: 6122497
    Abstract: An RF mixer provides extended dynamic range with reduced noise by utilizing degeneration inductors in the RF input section of a doubly balanced mixer. Degeneration inductors are also utilized in a mixer having a class AB input section. A current mirror in the class AB input section is also inductively degenerated for further noise reduction. The input section is biased by an all-NPN bandgap reference cell which is tightly integrated into the input section so as to reduce the power supply voltage required for the reference cell. The mixer can be optimized for wide input voltage ranges or low distortion.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: September 19, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 6121798
    Abstract: Comparator structures are shown which improve latching accuracy and enhance bandwidth for operations such as high-speed sampling in a variety of applications (e.g., analog-to-digital converters and automatic test equipment). The structures include an input differential pair of transistors having first and second control structures, a differential output amplifier and a clamp that limits the signal level of at least one of the first and second control structures. The clamp includes first and second Schottky diodes that are oppositely oriented and coupled between the first and second control structures. Altenatively one side of the diodes can be coupled to bias structures that respond to a threshold signal. Bias networks respond to a sampling threshold signal and stabilize biases in the input differential pair and the differential output amplifier.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: September 19, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Christopher McQuilkin
  • Patent number: 6118814
    Abstract: A method and system for providing adaptive filtering in a communication system. The method and system modify coefficients of a finite impulse response filter fed by a sequence of digital samples in accordance with an error signal in floating point format. The floating point error signal includes only a sign bit and an exponent term. The exponent term is added to an exponent term of an adaptation coefficient to produce a composite error signal. The adaptive filter is used as a linear adaptive equalizer and as an echo canceler.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: September 12, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Vladimir Friedman
  • Patent number: 6118326
    Abstract: A circuit that produces a gate drive voltage for a MOS transistor switch, that receives an input voltage "on" a source terminal, includes a first input that receives the input voltage, a second input that receives a bias voltage, and a voltage storage element. A first switch connects the voltage storage element to sample one of the input voltage and the bias voltage during a first of first and second non-overlapping time intervals. A second switch connects the voltage storage element to increase the sampled voltage by another of the input voltage and the bias voltage to the gate drive voltage during the second non-overlapping time interval, while maintaining the gate drive voltage less than a breakdown voltage of the MOS transistor switch. A third switch connects the voltage storage element to provide the gate drive voltage to the MOS transistor switch such that a gate-to-source voltage of the MOS transistor switch is maintained approximately constant.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: September 12, 2000
    Assignee: Analog Devices, Inc.
    Inventors: Lawrence Singer, Todd L. Books
  • Patent number: 6118301
    Abstract: An input/output driver circuit which provides a buffer interface between a functional digital circuit and a common bus for other digital circuits achieves high levels of voltage tolerance and compliance, while requiring only two power supply pins, by using two PMOS switching transistors between the circuit's output line and an output power supply terminal, rather than only one. To turn the transistors OFF, the output power supply voltage is applied to the gate of one of them and the output line voltage to the gate of the other. This assures that at least one of the transistors is fully OFF when desired, whether or not the output line voltage exceeds the output power supply level.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: September 12, 2000
    Assignee: Analog Devices, Inc.
    Inventors: Jaspreet Singh, Gregory T. Koker, Mark R. Newman
  • Patent number: 6107889
    Abstract: A charge pump circuit including current source circuits for maintaining the current sourced from an upper current source substantially equal to the current sunk by a lower current source. The current source circuits include a lower reference current source operable for defining a reference current through a first biasing transistor and a duplicate device in which an output current can be established proportional to the reference current therethrough. A complementary output device is provided for producing the upper current source along with a duplicate biasing device. The duplicate complementary biasing devices are such that the current through these devices is identical and equal to the reference current. A replication feedback loop coupled to both the common connected node of the complementary output devices and the common connected node of the complementary biasing devices operates to make the voltage at these two nodes substantially identical.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: August 22, 2000
    Assignee: Analog Devices, Inc.
    Inventors: Jonathan R. Strange, Ashish D. Shah
  • Patent number: 6107868
    Abstract: CMOS reference structures (e.g., voltage, current and resistance structures) are provided that are substantially insensitive to temperature, supply voltages and track fabrication processes. The structures include a V.sub.t -referenced source, a sensor and a summer. The source generates a source voltage and a feed-forward current that may have an error term and the sensor generates a feedback current that has a correction term that substantially offsets the error to stabilize a sum current. In different structure embodiments, voltage, current and resistance references are responsive to the stabilized sum current. The source, sensor and summer are preferably realized with MOSFETs whose channel width-to-length ratios are chosen to enhance the temperature insensitivity of the references.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: August 22, 2000
    Assignee: Analog Devices, Inc.
    Inventors: George F. Diniz, Ronald B. Gray, III
  • Patent number: 6104244
    Abstract: A rail-to-rail output circuit synthesizes a constant product output characteristic by replicating the current through a pull-up transistor and utilizing a translinear loop to drive a complementary pull-down transistor responsive to the replicated current. A smaller replication transistor shares a common V.sub.BE with the pull-up transistor so as to generate a scaled replication current that is proportional to the current through the pull-up transistor. The replication transistor is coupled to the base of the pull-down transistor through a bias circuit that forms a fast translinear loop with the pull-down transistor. An emitter follower transistor sevoes the loop so that the product of the currents through the pull-up and pull-down transistors is proportional to the square of a bias current. To reduce the turn-off time of the pull-down transistor, a second replication transistor is be connected with its base-emitter junction sharing the V.sub.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: August 15, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 6097239
    Abstract: A decoupled switched current temperature circuit with compounded .DELTA.V.sub.be includes an amplifier having an inverting input with corresponding non-inverting output and a non-inverting input with a corresponding inverting output; a PN junction connected to the non-inverting input through a first input capacitor and a voltage reference circuit is connected to the inverting input through a second input capacitor; a current supply includes a low current source and a high current source; a switching device applies the high current source to the PN junction and applies the low current source to the PN junction for providing the .DELTA.V.sub.
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: August 1, 2000
    Assignee: Analog Devices, Inc.
    Inventors: Evaldo Martino Miranda, Jr., Michael G. Tuthill, John Blake
  • Patent number: 6090678
    Abstract: A novel I.C. processing scheme for the fabrication of thin film features eliminates the wet etching step previously required, reducing the chip's minimum metal spacing and improving component matching capabilities and reliability. A thin film material is deposited and patterned, prior to a contact mask or platinum sputter/sinter/strip step, followed by the deposition of a protective layer. Contact mask and silicide metallization steps create contacts to the substrate, and a second contact mask step creates openings to the thin film features. The protective layer covering the thin film material allows a dry etch to be used for the final metal etch step, eliminating the need for a wet etch step and its attendant problems. The process requires no new design rules, and is easily adapted to existing products.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: July 18, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Mozafar Maghsoudnia
  • Patent number: 6087883
    Abstract: Multi-tanh cells constructed in accordance with the present invention provide improved input voltage range by utilizing resistors connected between the emitters of the transistors and the corresponding bias current sources. The resistor values and emitter area ratios are chosen to achieve substantially distortion-free transconductance functions over wide input voltage ranges. This improved input voltage range results in a corresponding improvement in dynamic range because the emitter resistances do not increase the noise significantly at low input voltage levels. In one embodiment, a separate resistor is connected in series with the emitter of each of the four doublet transistors. Another embodiment utilizes only a single bias current source and two emitter resistors to achieve better linearity and lower noise. To achieve higher effective emitter area ratios, an emitter follower scheme can be used to synthesize all or a portion of the area ratio.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: July 11, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 6087876
    Abstract: A time delay generator (20) includes a threshold generator (30), a ramp generator (32) and a comparator (34). The threshold generator provides a fixed threshold at one input of the comparator while the ramp generator provides at the other input a ramp signal whose slope is programmable. The ramp generator includes current switches (86 and 90) and a current converter (74). In response to input and range signals, the current switches provide a programmed input current and a programmed range current. The current converter generates a ramp current that is proportional to the range current and inversely proportional to the input current and couples that ramp current to an integrating ramp capacitor. The structure of the time delay generator facilitates noise filtering of the threshold signal and positioning of the threshold signal away from ramp nonlinearities.
    Type: Grant
    Filed: January 13, 1999
    Date of Patent: July 11, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Jeffrey G. Barrow
  • Patent number: 6087882
    Abstract: An isolator having a driver circuit which is responsive to an input signal to drive signals into a magnetic-field generator such as at least one coil. The generator is magnetically coupled to a sensor that includes spin-valve resistors which have resistance characteristics that are variable in response to the magnetic field generated by the generator. A receiver circuit incorporating a strobe generator converts the resistance changes to an output signal corresponding to the input signal.
    Type: Grant
    Filed: December 4, 1998
    Date of Patent: July 11, 2000
    Assignee: Analog Devices, Inc.
    Inventors: Baoxing Chen, Geoffrey T. Haigh, Alberto G. Comaschi
  • Patent number: 6088390
    Abstract: A method and system which combines a properly designed FEC and the periodic transmission of known symbols to obtain a desired error performance in a point-to-multipoint digital transmission system employing a DFE which induces error propagation. A transmitter unit includes a forward error correction encoder (FEC) which implements a code to information provided to an input of a data interleaver having block length N and interleaving depth D, and a data modulator which is coupled to an output of the data interleaver to receive a stream of data symbols. At least one receiver unit includes a decision feedback equalizer (DFE) which includes a feedback filter and provides an input to a data deinterleaver having block length N and interleaving depth D, and a FEC decoder which receives data from an output of the data deinterleaver. Sequences of known symbols of length at least equal to the length of the feedback filter are periodically added to the output of the data interleaver.
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: July 11, 2000
    Assignees: Analog Devices, Inc., Aware Inc.
    Inventors: Mark Russell, Vladimir Friedman, Stuart D. Sandberg
  • Patent number: 6084472
    Abstract: A biasing scheme for a multi-tanh amplifier improves the dynamic range of the amplifier by utilizing emitter degeneration resistors to reduce uncorrelated noise contributed by current source transistors used to bias the multi-tanh core. The current source transistors form part of a current mirror which can be coupled to a linear-in-dB cell through another current mirror to provide linear-in-dB gain control. An optimal version of the biasing scheme for a multi-tanh triplet minimizes noise at high gain while maximizing linearity and input signal range at low gain by varying both the absolute and relative magnitudes of the bias currents for the triplet core, thereby varying the shape of the transconductance function. The variable bias currents are provided by a multiple output current mirror in which the emitter of the center mirror transistor is connected directly to power supply ground, while the outer mirror transistors include degeneration resistors in their emitter paths.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: July 4, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 6074082
    Abstract: An analog multiplier includes a new circuit topology, which includes coupling an amplifier between the collector of one of the input transistors and the bases of the other two input transistors. The amplifier used in the new topology is a double emitter-follower. The collector currents in the other two input transistors are "forced" using the conventional topology but by a simple two transistor forcing circuit comprising a Darlington emitter-follower pair rather than the conventional operational amplifier. The simple forcing circuits allow the multiplier to be used in very low voltage applications having only a single supply voltage. Voltage to current converters can be used on the front end to convert voltage input signals to current input signals, which are then provided to the analog multiplier. The voltage to current converter uses a pre-biasing scheme to produce a linear relationship between the input voltages and the input currents across the entire voltage range of the input voltages.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 13, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 6072676
    Abstract: A protection circuit for an excitation current source protects against excessive compliance voltage by using a cascode transistor between the current source and an output terminal, and a transistor coupled to the output terminal and to the control lead of the cascode transistor to cause the cascode transistor to turn off if the voltage exceeds a threshold level.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: June 6, 2000
    Assignee: Analog Devices, Inc.
    Inventors: Chan Tran, Steven Martin, A. Paul Brokaw
  • Patent number: 6064277
    Abstract: A drive circuit for an oscillator having an LC tank reduces phase noise by maximizing the oscillation amplitude and minimizing the drive to the tank. The drive circuit utilizes a capacitive attenuator network for level shifting the oscillation signal before feeding it back to the drive transistors in the drive circuit, thereby allowing a large peak voltage swing across the tank without saturating the transistors. An adaptive control circuit controls the biasing of the drive transistors and reduces the drive to the tank when the maximum oscillation amplitude is reached so that the drive circuit replenishes just the minimum amount of energy lost in the tank during each cycle, thereby minimizing the coupling of active circuit noise into the tank.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: May 16, 2000
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 6064187
    Abstract: A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved by employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed, and by compensating the regulator to ensure a response that is flat after the occurrence of the peak deviation. The invention is applicable to both switching and linear voltage regulators.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: May 16, 2000
    Assignee: Analog Devices, Inc.
    Inventors: Richard Redl, Brian P. Erisman, Jonathan M. Audy, Gabor Reizik