Abstract: A method and system for quantizing an analog input signal. The method includes the step of concurrently feeding an input signal and a test signal to the sigma-delta modulator. The modulator provides a common filter for a composite signal comprising the test signal and quantization noise generated in the modulator. The modulator thus produces an output signal comprising a quantized input signal and the commonly filtered composite signal. The modulator output signal is fed to an adaptive quantization noise canceler. The adaptive quantization noise canceler combines the modulator output signal with a quantization noise nulling signal to produce a quantization noise compensated output signal.

Abstract: A fast, low output impedance, low-power clamp circuit for a switched complementary emitter follower includes a current mirror circuit and two transistors. In operation, high current is provided to allow for fast switching when turning off the complementary emitter follower. When the complementary emitter follower has been turned off, the clamp circuit reverts to low-power operation requiring much lower current while maintaining the complementary emitter follower in the off condition.

Abstract: A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory includes first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. Single, dual or quad data words of 32 bits each may be accessed in each of the memory banks during each clock cycle. The multiple data words may be transferred to one or both of the first and second computation blocks.

Abstract: A logic isolation circuit with high transient immunity has a link-coupled transformer assembly for providing isolation. An input circuit provides pulses that indicate rising and falling edges, and an output circuit on the isolated side of the barrier converts the signal with pulses back into a digital logic signal with rising and falling edges. An interrogation feature allows the output to be updated frequently. The logic isolator can be provided in a single module for use in a process control board, or it can be provided as multiple parts for mounting on a circuit board.

Abstract: A circuit that produces a gate drive voltage for a MOS transistor switch includes an input that receives a supply voltage, a regulated voltage generating circuit that produces a regulated voltage, and a voltage storage element. A first switch connects the voltage storage element to sample one of the supply voltage and the regulated voltage during a first of first and second non-overlapping time intervals. The second switch connects the voltage storage element to increase the sampled voltage by another of the supply voltage and the regulated voltage to the gate drive voltage during the second non-overlapping time interval. A third switch connects the voltage storage element to provide the gate drive voltage to the MOS transistor switch during the second non-overlapping time interval. The regulated voltage generating circuit produces the regulated voltage such that a high level of the gate drive voltage exceeds the supply voltage yet is maintained less than a breakdown voltage of the MOS transistor switch.

Abstract: A device for detecting with differential capacitors accelerations in more than one orientation through time-division multiplexing. A micromachined mass is movable along or about any axis in response to a force. The mass forms the common electrode of a set of differential capacitors, wherein the other electrodes of each differential capacitor are fixed. With each differential capacitor, one fixed electrode is set to one voltage and the other fixed electrode is set to a second voltage. The mass is connected to the input of an amplifier and to a switch for connecting the mass to a fixed voltage. The output of the amplifier is coupled to a demodulator for each orientation. A timing circuit activates one demodulator at a time. By toggling the voltages on the fixed electrodes of the differential capacitor corresponding to the active demodulator, the movement of the mass in the orientation corresponding to the active demodulator can be determined.

Abstract: An ADC system includes a sigma-delta modulator that receives an analog input and provides a first digital output and an analog output. An ADC, coupled to the sigma-delta modulator, receives the analog output as an input and provides a second digital output. A digital processor, coupled to the sigma-delta modulator and the ADC, receives the first and second digital outputs and provides a digital representation of the analog input.

Abstract: A comparison system compares a voltage which is proportional to absolute temperature S.sub.p to one which is equal to the sum of a conventional, uncorrected, bandgap cell voltage VBG and a proportional to absolute temperature voltage CT. The addition of CT to the uncorrected bandgap signal value yields a signal of the form Sp/(VBG+CT), which exhibits improved linearity over a signal of the form Sp/VBG, where VBG includes a Tln(T) term.

Abstract: A "lead-under-paddle" (LUP) leadframe employs a thermally conductive paddle/heat sink, the top side of which is adhered to an I.C. die with a thermally conductive adhesive. The inner portions of an I.C. package's leads extend along and are attached to the bottom side of the paddle with a thermally conductive and electrically isolating adhesive. Heat generated by the die is conducted to the leads and out of the package via the paddle/heat sink. The leads are in close contact with the paddle and die, reducing the leadframe's thermal resistance, increasing the amount of power that can be consumed by the die, and enabling a standard I.C. package to accommodate a paddle and die having larger respective surface areas.

Abstract: An low dropout voltage regulator (LDO) drive reduction circuit detects when the LDO's output voltage is going out of regulation due to a falling input voltage while the output is lightly loaded, and reduces the drive to the pass transistor in response. This action prevents the LDO's ground current from rising unnecessarily. The drive reduction circuitry directly monitors the voltage across the pass transistor; when above a predetermined threshold voltage which is typically well-below the LDO's specified dropout voltage, the pass transistor drive is permitted to vary as necessary to maintain a specified output voltage. If the monitored voltage falls below the threshold voltage, indicating that the input voltage is falling and the output is lightly loaded, the drive reduction circuit reduces the drive current, which would otherwise get increased in an attempt to restore the output voltage.

Abstract: A digital signal processing system includes a cluster of processors and a host. A host can access each of the processors through an external bus system that interconnects the host with each of the processors. An external port of each of the processors operates at one of a local clock frequency and host clock frequency, the local clock frequency and host clock frequency being asynchronous with one another. The host operates at the host clock frequency. Upon a host access of one of the processors, the clock frequency of operation of the external parallel port of each processor automatically is controlled to operate at the host clock frequency. In an embodiment, each processor also includes a core processor that operates at a core clock frequency that is a multiple of the local clock frequency, asynchronous with the host clock frequency. Thus, the speed of operation of the core processor and that of the external parallel port can be optimized independently.

Abstract: A method and apparatus for operating an asymmetric digital subscriber loop modem system. A modem at a central office transmits information to a modem at a remote terminal on a down-stream signal having a predetermined bandwidth and the modem at the remote terminal transmits information to the modem at the central office on an up-stream signal having a bandwidth lower than the predetermined bandwidth of the down-stream signal. Digital samples of the up-stream signal in the central office modem are produced. Digital samples representative of an estimated echo signal in the central office modem are also produced. The digital samples of the up-stream signal and the digital samples representative of an estimated echo signal are both fed to a subtractor at the same rate. In a preferred embodiment, the up-stream signal is oversampled (i.e., is sampled at a rate greater than the Nyquist sampling rate) in producing the digital samples thereof. Samples of the down-stream signal are fed to an echo cancellation filter.

Abstract: A trimmable voltage regulator feedback network is arranged as a voltage divider: series-connected resistors are connected between the divider tap and the regulator's output voltage and a fixed resistance is connected between the tap and ground. Severable links are connected across at least two resistors above the tap to allow the regulator output voltage to be trimmed in linearly independent increments with each severed link, thereby simplifying the task of determining which links to sever to attain a desired output voltage. A trimmable resistance is inserted between the divider tap and the circuit being driven to enable the impedance of the network to be adjusted. A regulator including the novel feedback network can provide a temperature-compensated output over the full range of selectable output voltages.

Abstract: An apparatus and method for protecting integrated circuits from electrical overstress and eletrostatic discharge is provided. The apparatus includes a primary EOS/ESD protection device and a feedback circuit. The feedback circuit maintain the primary EOS/ESD protection device in an off state during normal operation of the integrated circuit and switches the primary protection device to an state when an EOS/ESD event occurs at a first input pad with respect to a second input pad of the integrated circuit.

Abstract: A switched-transconductance circuit used in a multiplexer forming a part of a crosspoint switch includes integrated T-switches that are enabled when the transconductance stage is not enabled. The transconductance stage is selectively enabled by controlling a split-tail current source driving a differential pair of input transistors. When the transconductance stage is disabled (1) a pair of switches connected between the collectors of the differential pair and a positive voltage supply node are enabled, (2) a pair of cascode transistors connected between the collectors of the differential pair and output leads of the circuit are reversed biased by the positive supply voltage passing through the pair of switches, and (3) a switch is enabled between a common emitter node of the differential pair and a low impedance constant voltage node.

Abstract: In a switched-capacitor input sampling structure, a resistor connected in series with the input structure, but after the output of the input switch limits the noise bandwidth of the input structure. The selected placement of the resistor does not appreciably limit the slewing or settling time of downstream circuit elements, resulting in a low noise bandwidth, high speed system.

Abstract: A high performance digital signal processor includes a bidirectional communication port for communication with an external device. The bidirectional communication port includes a first transmitting circuit for transmitting to the external device a first clock on a first control line in a transmit mode and for transmitting data words on plural data lines in synchronism with the first clock, and a first receiving circuit for receiving a first acknowledge signal on a second control line in the transmit mode. The communication port further includes a second receiving circuit for receiving a second clock on the second control line in a receive mode and for receiving data words on the data lines in synchronism with the second clock, and a second transmitting circuit for transmitting a second acknowledge signal on the first control line in the receive mode. The communication port further includes switching means for switching between the transmit mode and the receive mode.

Abstract: A digitally controlled variable transconductance amplifier system including first and second input means for receiving first and second input voltages of opposite phase; first and second output means; a voltage to current converter system responsive to the input voltage and including a reference voltage to current converter and a plurality of voltage to current converters each having a different gain relative to the reference voltage to current converter such that the total gain of the voltage to current converters is less than that of the reference converter; each of the converters providing a pair of oppositely phased converter output currents; and a summing system including a reference switching circuit and a plurality of switching circuits, the reference switching circuit and the switching circuits being interconnected with said reference converter and the plurality of voltage to current converters, respectively, the summing system being responsive to a digital control signal for operating each of the swi

Abstract: A dual-tunable direct digital synthesizer is provided with a programmable frequency multiplier that multiplies a relatively low frequency fixed clock signal F.sub.clk so that the output frequency F.sub.o of the waveform is:F.sub.o =(F.sub.n /2.sup.N).times.(M.times.F.sub.clk)where N is the resolution of the digital control word, the tuning word F.sub.n is the value of the N-bit control word, M is the multiplication factor and M*F.sub.clk is the DDS clock frequency. The multiplication factor and, hence, the DDS clock can be reduced to track changes in the output frequency thereby lowering the average power consumption. Because the synthesizer can generate the same output frequency using different tuning word-to-DDS clock ratios, it can be tuned for optimum SFDR over a narrow band around the desired output frequency. In other words, an "enhanced dynamic range band" in the harmonic and spurious performance can be mapped out for each frequency in the bandwidth.

Abstract: An automatic and integrated mechanical and electrical accelerometer test system including a test fixture for holding the accelerometers to be mechanically and electrically tested; a handler subsystem for automatically feeding the accelerometers to the test fixture; a shaker subsystem for mechanically testing the accelerometers, the shaker subsystem linked to the test fixture, the shaker subsystem automatically vibrating the test fixture; and a tester for electrically testing the accelerometers while the accelerometers are vibrating.