Abstract: A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory includes first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. Single, dual or quad data words of 32 bits each may be accessed in each of the memory banks during each clock cycle. The multiple data words may be transferred to one or both of the first and second computation blocks.

Abstract: An integrated circuit assembly is formed with an integral power supply decoupling capacitor for monolithic circuitry in a semiconductor substrate by using the substrate itself as one plate of the capacitor. A dielectric is formed on the "back" side, or surface, of the substrate (i.e., the surface opposite the surface in which component structures are formed) such as by growing a native oxide thereon. Using a conductive epoxy, the back side of the substrate (actually, the dielectric layer thereon) is then attached to a conductive foundation member, which forms the other plate of the capacitor when a potential is applied across the substrate and the foundation member. The conductive foundation member also may be connected to a heat sink structure integral with the package. The heat sink may extend through a window in the package, providing a path and surface via which heat may be transferred to an external heat sink if a larger heat sink mass is needed.

Abstract: A method and apparatus for digital-to-digital conversion using sigma-delta modulation of the temporal spacing between digital samples. The method and apparatus of the present invention provides for sigma-delta modulation of the time base such that noise produced by NONUNIFORM sampling are frequency-shaped to a region (i.e., shifted to higher frequencies where it can be removed by conventional filtering techniques. In one embodiment, the digital data is interpolated (16) by fixed ratio and then decimated (21) under control of a first sigma-delta modulated frequency selection signal (26) that represents, on average, the data rate of the incoming digital data stream. Thereafter, the digital data is interpolated (30) under control of a second sigma-delta modulated frequency selection signal (46) that represents, on average, the data rate of the digital data to be output by the converter and then decimated (40) by a fixed ratio.

Abstract: A circuit for decoding an input signal includes a measurement circuit having an input to receive a timing clock signal that is asynchronous with clocking of the input signal, to measure duration of a plurality of pulses received on the input signal in relation to frequency of the timing clock signal and a decode circuit to decode the input signal into digital data. In one embodiment, the circuit may include a servo mechanism for generating the timing clock signal to have a frequency that varies in response to variations in frequency of clocking of data on the input signal. The servo mechanism may include a digitally controlled oscillator and a feedback circuit, to control the digital frequency of the digitally controlled oscillator in response to variation of clocking of data on the input signal. The invention permits use of all digital components for decoding digital audio data encoding using biphase-mark encoded data according to the SPDIF or AES/EBU standards.

Abstract: A printed circuit balanced to unbalanced (balun) transformer. The balun includes strip circuitry having first, second and third conductors. The first conductor provides a primary inductor of the transformer. The primary inductor has a first electrode adapted for coupling to an unbalanced transmission line and a second electrode electrically connected to the ground plane conductor. The second conductor provides a first secondary inductor of the transformer. The first secondary inductor is inductively coupled to a first portion of the primary inductor. A first electrode of the first secondary inductor is electrically connected to the ground plane conductor and a second electrode of the first primary inductor coupled to a first of a pair of output ports. The conductor provides a second secondary inductor of the transformer. The second secondary inductor is inductively coupled to a second portion of the primary inductor.

Abstract: A variable gain amplifier includes an input transconductor having a transconductance that is variable in response to a first control signal, an output circuit having a transresistance that is variable in response to a second control signal and a gain controller responsive to a gain control signal x for providing the first and second control signals to the input transconductor and the output circuit. The amplifier has a voltage gain equal to the product of the transconductance and the transresistance. When the first control signal is a function (1+x) of the gain control signal and the second control signal is a function (1-x) of the gain control signal, the voltage gain of the amplifier is approximately an exponential function of the gain control signal.

Abstract: A power-on reset circuit initiates a reset signal when the circuit's power supply voltage is low, and terminates the signal in response to the supply voltage exceeding a reset termination threshold that is based upon the greater of the threshold voltages for p-channel and n-channel FETs employed in the circuit. The reset termination threshold is preferably the sum of the greater FET threshold plus a safety margin, with the termination delayed by a predetermined period to ensure an adequate reset period, and a hysteresis feature added to ensure a stable reset termination.

Abstract: A flux concentrator made of a high permeability material is enclosed in a semiconductor package with a magnetic sensing integrated circuit to improve the uniformity and magnitude of the magnetic field sensed by the sensor.

Abstract: A micromachined device is provided that establishes select dimensional relationships between micromachined structures to achieve correlation in dimensional variation among these structures. Such dimensional relationships are achieved through consistent spacing between desired operating structures and by adding new structures (i.e., dimensional control structures) which provide additional consistent spacing at desired locations within the micromachined device.

Abstract: A method and apparatus for providing a sub-ground plane for a micromachined device. The sub-ground plane is formed in or on the substrate. Above the sub-ground plane is a dielectric and then a discontinuous conductive layer used for interconnects for parts of the micromachined device. A movable microstructure is suspended above the interconnect layer. A conductive layer can be suspended above the movable microstructure. In one embodiment, the sub-ground plane is diffused into the substrate or a well in the substrate, and is of an opposite type from the type of silicon into which it is diffused. Alternatively, the sub-ground plane is formed from a conductive layer, deposited over the substrate before the layer used for interconnects.

Abstract: A method for forming an isolation wall in a silicon semiconductor substrate wherein a trench is etched into the silicon using a hard mask, a layer of silicon dioxide is formed on the side walls of the trench, a filling of polysilicon is placed in the region between the side wall layers, the polysilicon is planarized by etching while the hard mask remains in place, and the hard mask then is stripped from the silicon, permitting field oxide to be grown over the trench region.

Abstract: Acoustic signals received by the ears are controlled by feeding back and filtering the signal to be applied to the speaker, rather than by use of a feedforward filter. The feedback filter may incorporate an electrical model of the speaker-to-ear transfer function to force the ear signals to a desired ratio of amplitudes and phases as a function of the frequency. The signals to be output to the right and left channels are fed back through a filter to obtain a feedback signal. The feedback signal is subtracted from one input channel and added to the other input channel to provide the output signals. This technique may be used both in stereo spreading and in three-dimensional localization of a monaural sound source. By using feedback instead of feedforward, the system can be readily adapted to different playback environments. Through a simple adjustment of the electrical model of the speaker-to-ear transfer functions, this system automatically provides the desired ear signals.

Abstract: A differential line driver having a pair of transistors arranged as a differential pair for driving a transmission line with a differential logic output signal produced in accordance with a differential logic input signal fed to the base electrodes of the pair of transistors. The differential line driver includes circuitry for suppressing EMI emissions generated by common mode voltage switching transients produced at the collector electrodes of the pair of transistors in response to changes in the differential logic input signal. The common mode voltage switching transient suppression circuitry includes a pair of additional transistors. The differential logic input signal is fed to base electrodes of the additional transistors, and through such additional transistors, to the base electrodes of the pair of transistors of the differential pair. In one embodiment of the invention, the additional transistors are connected in a Darlington pair arrangement with the pair of transistors of the differential pair.

Abstract: A sampling capacitor interface circuit for storing charge on a sampling capacitor related to a sample of an input signal voltage during a charging phase and to transfer the stored charge to an output during a charge transfer phase, such input signal having bipolar voltages within a range above and below an input signal common mode voltage. The interface circuit includes a transistor having: an input electrode fed by the input signal; an output electrode coupled to the sampling capacitor; and, a control electrode. A controller is provided for producing a control signal having a first voltage during the charging phase and a second voltage during the charge transfer phase, such voltages being a unipolar voltage referenced to the input signal common mode voltage.

Abstract: A micromachined device has a plurality of rotationally dithered masses that are used to sense acceleration. To eliminate common modes, the masses are dithered in an equal and opposite manner. To help maintain this relationship between the movement of the masses, a coupling fork provides minimal resistance to anti-phase movement and substantial resistance to in-phase movement. Electrodes are used to detect changes in capacitance between the masses and the substrate resulting from rotation of the device about a radial axis of a mass. These electrodes are electrically connected to eliminate gradients that are caused by external forces and manufacturing differences. Four masses or more can be provided, arranged in a two-dimensional array, such as a square or hexagon with a coupling fork provided between each pair of masses, and with electrodes connected to eliminate gradients.

Abstract: A comb filter for use in a video decoder is described. The comb filter includes a line memory for storing as successive pairs of U and V samples of a decoded video signal corresponding to a previous horizontal line of video information and a line memory for storing a second previous horizontal line of video information. The filter also includes a circuit to calculate an average value of both U and V from a previous sample and a corresponding sample from a previous line. The filter also includes a circuit for calculating a correction term for each one of the averages. The correction term is calculated from the opposite color component as was used to calculate the average value.

Abstract: A high impedance node of a transimpedance stage drives the input of a unity-gain forward buffer. A unity-gain integrated back-buffer is enabled to drive the high-impedance node from the output of the forward buffer when the forward buffer is disabled. A voltage from the forward buffer limits the reverse-biasing of all transistors in the back-buffer when the back buffer is disabled, and a voltage from the back-buffer limits the reverse-biasing of all transistors in the forward buffer when the forward buffer is disabled. The output-driver transistors of the forward buffer are bootstrapped to the output voltage through resistors which, when the forward buffer is enabled, bias pre-driver transistor coupled to the output-driver transistors. Neither the forward buffer nor the back-buffer consume a significant amount of power when not enabled.

Abstract: A switching bandgap reference circuit with compounded .DELTA.V.sub.BE includes an amplifier having an output, an inverting input and a non-inverting input; a first PN junction connected to the non-inverting input; a second PN junction connected to the inverting input through an input capacitor; a low current source and a high current source; a switching device for applying in the auto zero mode the low current source to a first terminal of the first PN junction and the high current source to a first terminal of the second PN junction for establishing the V.sub.BE, of the first junction at both the inputs of the amplifier and for applying in the valid reference mode the high current source to the first terminal of the first PN junction and the low current source to the first terminal of the second PN junction for establishing the positive .DELTA.V.sub.BE, of the first PN junction to both the inputs of the amplifier and applying the negative .DELTA.V.sub.

Abstract: Emitter widths of 0.3 .mu.m on double polysilicon bipolar transistors are achieved using O.8 .mu.m photolithography and a double spacer process. The emitter width reduction is confirmed with structural and electrical measurements. The double-spacer device exhibits superior low current f.sub.T and f.sub.max.

Abstract: In a multi-stage, multi-residue interpolating analog-to-digital converter (ADC), which is suitable for pipelined implementation, inputs of at least three amplifiers are "leapfrog" switched to adjacent nodes of a first interpolation ladder having discrete voltage levels established thereon. Pairs of the amplifiers drive second interpolation ladders to establish additional discrete voltage levels (in a nominal and an overlap conversion region) at nodes of the second interpolation ladders. A bank of comparators compares a predetermined threshold voltage, e.g., ground, to several of the discrete voltage levels at the nodes of the first interpolation ladder. The switches controlling which inputs of the amplifiers are connected to which nodes of the first interpolation ladder are controlled by a logic circuit which is driven by outputs of the bank of comparators. Alternatively, the bank of comparators compares an input voltage of the ADC to voltage levels established by the first interpolation ladder.