Abstract: A switched-capacitor DAC system includes two switched-capacitor DACs and a load circuit. The switched-capacitor filter of the first DAC samples a reference voltage source, which produces a reference voltage, at a first rate and the switched-capacitor filter of the second DAC samples the reference voltage source at a second rate, greater than the first rate. The load circuit samples the reference voltage source at a rate such that the level of the reference voltage is the same each time a sample is taken. The load circuit effectively equates the sampling of the two filters and substantially eliminates problems related to gain errors and low frequency quantization noise.

Abstract: An error correction testing system and method for a multistage A/D converter includes a testing device for disabling the correction circuit and indicating the code transitions of the first A/D converter relative to the code transitions of the second A/D converter representing error in the first A/D converter.

Abstract: Bipolar transistors and MOS transistors on a single semiconductor substrate involves depositing a single layer of polysilicon on a substrate, including complementary transistors of either or both types, and a method for fabricating same. The devices are made by depositing a single layer of polysilicon on a substrate and etching narrow slots in the form of rings around every bipolar emitter area, which slots are thereafter filled with an insulating oxide. Then, emitters and extrinsic base regions are formed. The emitters are self-aligned to the extrinsic base regions. An optional cladding procedure produces a surface layer of a silicide compound, a low resistance conductor. The resulting structure yields a high-performance device in which the size constraints are at a minimum and contact regions may be made at the top surface of the device.

Abstract: A high gain transistor amplifier with internal balancing bias having a common mode input range which includes a supply rail includes a differential to single-ended converting input stage including at least one pair of transistors, each transistor having first and second current terminals and a control terminal; input means for providing an input signal to the first current terminals of the transistors; a voltage amplifier stage for providing an amplified output of the input signal, the voltage amplifier stage including at least one transistor having a control terminal; and a biasing circuit responsive to the voltage amplifier stage for maintaining balanced currents between the control terminal of the voltage amplifier stage and the control terminals of the differential to single-ended converting input stage, the biasing circuit being connected to the second current terminals of each transistor pair and the voltage amplifier stage being connected to one of the second current terminals so that the first termina

Abstract: A scrambler for use with thermometer-code digital signals and having a number of interconnected identical switching cells in the form of swapper cells with two inputs and two outputs. A control signal determines whether the inputs are connected directly or reversely to the outputs. The control signal is developed by logic circuitry which receives as inputs the two swapper cell input bits and a state bit representing the integrated difference of past swapper output signals.

Abstract: CRT control apparatus for use in high-resolution graphic display equipment of the type including a graphics processor and a frame buffer having storage banks for storing digital signals representing the color intensities of red, green and blue colors of pixels to be presented on the CRT screen. The apparatus includes an MOS integrated-circuit (IC) chip which serves as the master timing control for the entire CRT sub-system, including timing of the read-out of pixel signals from the frame buffer, loading of the pixel signals into latches on the MOS chip, and multiplexing of the signals stored in the latches. Digital signals representing the color intensities are directed to corresponding DACs which generate the analog intensity color signals for the electron guns of the CRT.

Abstract: A method and apparatus for addressing a memory space as a row and column matrix so as to allow the single matrix to store data of various widths, e.g., 16, 32 and 48-bits, with a minimum of wasted memory space. A specified number of the LSBs of the address are used to select a row in the matrix, while the remaining MSBs are used to select a columnar portion. Additional bits indicate the length of the data selected. The MSBs of the address and the additional bits indicating the length of the word accessed are used as inputs to a combinational logic circuit, the outputs of which are coupled to control switches for activating only the appropriate columnar portion of the matrix. Thus, although the LSBs of the address used to select the row activate every bit in that row, the switches are controlled so as to connect to the bus only the bits in that row corresponding to the selected columnar portion.

Abstract: A two terminal temperature transducer which controls its operating current to indicate the temperature, by producing a linear response to temperature which can be set to extrapolate to a desired temperature. The transducer including circuitry which controls its operating current to be linearly proportional with temperature. The circuitry operates to produce a first reference voltage which is proportional to absolute temperature, produce a second reference voltage which is complementary to absolute temperature, generate a voltage drop corresponding to the operating current, compare the voltage drop to a temperature sensitive voltage corresponding to the difference between the first reference voltage and the second reference voltage, and adjust the operating current so as to equilibrate the voltage drop and the temperature sensitive voltage.

Abstract: A resistor ladder (10) includes a plurality of series resistors (16,18,20,22,24,26,28) connected in series with each other between a first terminal (12) and a second terminal (14). A plurality of shunt resistors (60,62,64,66, 68,70) are connected between junctions (48,50,52,54,56) of adjacent series resistors and the second terminal (14). The series resistors (16,18,20,22,24,26,28) and shunt resistors (60,62,64,66,68,70) are formed on a substrate (80) as film resistors which blow open at a predetermined current density. The shunt resistors (60,62,64,66,68,70) have a smaller cross-sectional area than the series resistors (16,18,20,22,24,26,28) such that they successively blow open from the first terminal (12) toward the second terminal (14), while the series resistors (16,18,20,22,24,26,28) do not blow open, as a progressively increasing voltage is applied between the first terminal (12) and the second terminal (14).

Abstract: An integrated-circuit (IC) chip formed with a fault-protected switch comprising three MOS transistors in series. Each transistor is placed in a corresponding tub of the IC chip. Each of these tubs is electrically isolated from all other sections of the IC chip, so that the MOS transistors are isolated from one another and from the chip voltage supplies.

Abstract: An analog-to-digital converter (ADC) having three cascaded A/D stages of the "flash" type. In the first stage, the analog signal is compared with a set of threshold reference voltages so as to develop a set of most-significant bits and to produce two analog residue signals: (1) a normal residue corresponding to the difference between the analog input and the reference voltage next below the analog input, and (2) a second residue corresponding to the difference between the analog input and the reference voltage next above the analog signal level. These two residue signals are amplified and directed to the second A/D stage. The sum of the residue signals equals one LSB of the first A/D stage, so that the two residues supply to the second stage information about the quantization error of the previous stage as well as the quantization step size to be used to define full-scale at the second stage. The second A/D stage develops a set of less-significant bits and two more residue signals for the third A/D stage.

Abstract: A analog-to-digital converter (DAC) comprises a plurality of circuit stages. Each of the circuit stages includes a switching circuit having an assertive circuit portion and a complementary circuit portion. A first transistor and a first resistor constitute the assertive circuit portion, which is electrically connected between a first reference voltage supply conductor and a switch output node inside the DAC. In a similar fashion, a second transistor and a second resistor constitute the complementary circuit portion, which is also electrically connected between a second reference voltage supply conductor and the switch--output node. The first and second resistors, and the resistor in the resistor network which is electrically connected to the switch output node, are substantially equal in ohmic values.

Abstract: A system includes a digital-to-analog converter circuit and a calibration circuit. The digital-to-analog converter circuit includes a gain control circuit providing volume adjustment. The system includes a calibration mode and a normal mode of operation. During calibration, a correction value associated with the gain control circuit is measured by the calibration circuit and stored. During normal operation, the stored correction value is combined with the input before provision of the same to the DAC circuit such that, for a predetermined input of midscale code, the desired system output remains constant despite any change in the volume setting of the gain control circuit.

Abstract: An emulation system used to debug software for a digital signal processor (DSP) includes a built-in digital signal analyzer which operates upon the same digital signals as those presented directly to and outputted by the DSP, bypassing the signal converters used to convert an input analog signal to digital format and the output digital signal to analog format. A host computer communicates with the digital signal analyzer via firmware in a control processor and personality board, or is alternately connected directly with the analyzer. Communications between the digital signal analyzer and the DSP are through the same contact probe as that used for the emulation software. The analyzer may be used to trigger a software function within the emulator based upon the real-time signal from the DSP, and is also capable of interpolating between successive digital values of an analyzed signal for display purposes.

Abstract: A maximum likelihood detector for a continuous time disk drive read channel includes a dynamic threshold updating circuit for a maximum likelihood detector using both positive and negative comparators for detecting the positive and negative peaks of an input signal; this includes comparing the input signal with at least one present dynamic threshold to produce positive and negative binary gating signals; a control circuit responsive to the binary gating signals, to the input signal, and to the peak detector circuit which identifies qualified input signal peaks; and a threshold update circuit responsive to the identification of qualified input signal peaks, which adjusts the present dynamic threshold by the difference between the input signal and the present dynamic threshold to obtain the next dynamic threshold.

Abstract: A method and apparatus for forming bridges between surfaces of a suspended microstructure and other surfaces of the suspended microstructure or particularly placed anchors on the die in order to increase the stiffness and lateral strength of the microstructure during fabrication. Once fabrication is completed, the bridges are cut by a laser thus fully releasing the microstructure into its final suspended and resilient condition.

Abstract: An IC chip formed with an analog-to-digital converter having a switched-capacitor programmable gain stage and employing a switched-capacitor sigma-delta modulator. The chip includes pins to receive a number of different audio input signals which are selectively connectible to buffer amplifiers the outputs of which are directed to a switch to select one output for further processing. The selected buffer amplifier output is d-c coupled to an input signal terminal of a switched-capacitor programmable gain stage. The output of this gain stage is coupled to an output stage including an op-amp and associated switched-capacitor circuitry. The programmable gain stage has a reference input terminal which is connected through an IC chip pin to an external capacitor the other electrode of which is returned to signal common.

Abstract: An output curvature correction is provided for a band-gap reference circuit that exhibits a temperature dependent output error in the form of k.sub.1 T - k.sub.2 Tln(k.sub.3 T) in the absence of the correction. A substantially constant collector current is driven through a correction transistor and used in connection with a proportional to absolute temperature (PTAT) transistor collector current in the uncorrected circuit. The difference between the base-emitter voltages for the two transistors has the form -k.sub.1 'T + k.sub.2 'ln(k.sub.3 'T.sub.). This voltage differential is scaled by an appropriate selection of resistor ratios and combined with the uncorrected circuit output to provide a corrected output that is substantially insensitive to temperature variations.

Abstract: The n-bit coefficients of a FIR filter are encoded into m-bit digital words that represent selected bits of the original coefficients, where m is less than n, together with shift words that represent the order of the selected bits within the original n-bit coefficients. A software .sigma.-.DELTA. modulator is used to implement the encoding. The reduction in coefficient bits allows for a corresponding reduction in hardware multiplier capacity required to convolve the encoded coefficients with input data. The quantization error from the encoding is shaped to a higher frequency range that can later be filtered out. The coefficients are preferably encoded into a format that coincides with the data format employed by the multiplier, such as by using a Robertson's algorithm to encode to a modified Booth format.

Abstract: An integrated circuit including a comparator having two output states and being responsive to a voltage developed across a shunt in the circuit so that the comparator assumes one of its two output states when the voltage developed across the shunt is greater than a threshold switching voltage and the other of its two output states when the voltage developed across the shunt is less than the threshold switching voltage. The integrated circuit additionally includes a threshold switching voltage sensitivity control circuit, coupled to and controlling the comparator, for controlling a sensitivity of the threshold switching voltage to changes in a supply voltage of the lamp circuit and for controlling a sensitivity of the threshold switching voltage to changes in temperature of the integrated circuit.