Abstract: An apparatus, method, and system for identifying and obtaining information related to a substrate support and/or a pre-heat ring in a process chamber via imaging and image processing. In an embodiment, a substrate support is provided. The substrate support generally includes a top surface configured to receive a substrate in a process chamber and a marking feature disposed on the top surface of the substrate support, the marking feature configured to be detectable by an imaging apparatus coupled to the process chamber to provide information related to the substrate support via imaging when the substrate support is disposed within the process chamber.

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

Abstract: A display screen includes a backplane, an array of light-emitting diodes electrically integrated with the backplane, the array of light-emitting diodes configured to emit UV light in a first wavelength range, and a plurality of isolation walls formed on the backplane between adjacent light-emitting diodes of the array of light-emitting diodes with the isolation walls spaced apart from the light-emitting diodes and extending above the light-emitting diodes. The plurality of isolation walls include a core of a first material and a coating covering at least a portion of the core extending above the light-emitting diodes. The coating is an opaque second material having transmittance less than 1% of light in the first wavelength range.

Abstract: Implementations described herein provide a substrate support assembly which enables both lateral and azimuthal tuning of the heat transfer between an electrostatic chuck and a heater assembly. The substrate support assembly comprises an upper surface and a lower surface; one or more main resistive heaters disposed in the substrate support; and a plurality of heaters in column with the main resistive heaters and disposed in the substrate support. A quantity of the heaters is an order of magnitude greater than a quantity of the main resistive heaters and the heaters are independently controllable relative to each other as well as the main resistive heater.

Abstract: Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise an oxidize layer on a semiconductor material between source regions and drain regions of the device. The method includes radical plasma oxidation (RPO) of semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: A method includes initiating a connection with a semiconductor manufacturing system. The method further includes generating a set of tool data items associated with the semiconductor manufacturing system. The method further includes providing a graphical user interface (GUI) presenting the set of tool data items associated with the semiconductor manufacturing system and receiving and via the GUI, user input selecting one or more of the tool data items. The method further includes adding configuration data associated with one or more of the tool data items to a data collection plan. The method further includes validating the configuration data by locating, in the manufacturing system, a configuration data file associated with the configuration data. The method further includes executing one or more data collection operations based on the data collection plan.

Abstract: Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.

Abstract: A polishing assembly includes a rotatable platen to support a polishing pad, a polishing liquid delivery arm having an enclosure open at a bottom thereof and one or more ports to deliver a polishing liquid and a cleaning fluid downwardly through an interior space of the enclosure onto the polishing pad, and a delivery arm cleaning tool removably attached to the polishing liquid delivery arm, the cleaning tool extending below the delivery arm and having a delivery arm-facing surface shaped such that the cleaning tool directs the cleaning fluid from the polishing liquid delivery arm on to a surface of the enclosure of the polishing liquid delivery arm.

Abstract: Ampoules including a housing, a lid and a floating structure are described. The floating structure includes a float with a volume determined to displace a predetermined volume of liquid within the ampoule. An outlet channel extends from the top surface of the float. A baffle is positioned along the length of the outlet channel and creates a saturation zone between the baffle and the float.

Abstract: A sensor can be configured to measure wafer bowing characteristics associated with a bow of a wafer after a first fabrication process is performed on the wafer in a first processing chamber and before a second fabrication process is performed on the wafer in a second processing chamber. A transfer chamber, including the sensor, can be coupled to a first process chamber and a second process chamber. The wafer bowing characteristics can be used by a controller to determine recipe parameters. The recipe parameters can be used by the controller to control environmental conditions in the transfer chamber and/or processing chamber and cause the processing chamber to perform its associated fabrication process using the recipe parameters.

Abstract: An apparatus that includes an end effector for handling and transporting wafers, the end effector including: a base portion having a first end adapted to be attached to a robot; a wafer support platform having a surface to support a wafer, a slidable joint coupling the base portion to the wafer support platform; and a sensor configured to detect when the wafer support platform slides relative to the base portion beyond a predetermined distance.

Abstract: Exemplary semiconductor processing methods may include providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of a silicon-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor. The contacting may etch a feature in the layer of silicon-containing material. A substrate support pedestal temperature may be maintained at less than or about ?20° C. during the semiconductor processing method.

Abstract: Exemplary methods of coating a metal-containing component are described. The methods are developed to increase corrosion resistance and improve coating adhesion to a metal substrate. The methods include forming a bonding layer on a metal substrate, where the bonding layer includes an oxide of a metal in the metal substrate. The coating methods further include depositing a stress buffer layer on the bonding layer, where the stress buffer layer is characterized by a stress buffer layer coefficient of thermal expansion (CTE) that is less than a metal substrate CTE and a bonding layer CTE. The coating methods also include depositing an environmental barrier layer on the stress buffer layer, where a ratio of the metal substrate CTE to an environmental barrier layer CTE is greater than or about 20:1, and where the environmental barrier layer includes silicon oxide. The metal-containing components may be used in fabrication equipment for electronic devices.

Abstract: Exemplary semiconductor processing methods may include providing a first silicon-containing precursor and a second silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The first silicon-containing precursors may include Si—O bonding. The methods may include forming a plasma of the first silicon-containing precursor and the second silicon-containing precursor in the processing region. The methods may include forming a layer of silicon-containing material on the substrate. The layer of silicon-containing material may be characterized by a dielectric constant less than or about 3.0.

Abstract: Embodiments of the present disclosure are directed to selective etching processes. The processes include flowing a precursor comprising one or more of an interhalogen, a halogen-containing species, a pseudohalogen species, a mixture of one or more of the interhalogen, the halogen-containing species, or the pseudohalogen species and an amine or a phosphine, or a mixture of one or more of the interhalogen, the halogen-containing species, or the pseudohalogen species with a sulfur-containing species, into a semiconductor processing chamber containing a substrate, and forming an activated species of the precursor to etch a substrate. The substrate has a plurality of alternating layers of silicon oxide and silicon nitride thereon and a trench formed through the plurality of alternating layers. The silicon nitride layers are selectively etched relative to the silicon oxide layers at an etch selectivity of greater than or equal to 500:1.

Abstract: Methods of filling a feature on a semiconductor substrate may include performing a process to fill the feature on the semiconductor substrate by repeatedly performing first operations. First operations can include providing a silicon-containing precursor. First operations can include contacting the substrate with the silicon-containing precursor to form a silicon-containing material within the feature defined on the substrate. First operations can include purging the semiconductor processing chamber. First operations can include providing an oxygen-and-hydrogen-containing precursor. First operations can include contacting the substrate with the oxygen-and-hydrogen-containing precursor to form a silicon-and-oxygen-containing material within the feature defined on the substrate.

Abstract: An electronic device manufacturing system capable of obtaining metrology data generated using metrology equipment located within a process chamber that performs a deposition process on a substrate according to a process recipe, wherein the process recipe comprises a plurality of setting parameters, and wherein the deposition process generates a plurality of film layers on a surface of the substrate. The manufacturing system can further generate a correction profile based on the metrology data. The manufacturing system can further generate an updated process recipe by applying the correction profile to the process recipe. The manufacturing system can further cause an etch process to be performed on the substrate according to the updated process recipe.

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

Abstract: Embodiments of the present disclosure relate to optical devices for augmented, virtual, and/or mixed reality applications. In one or more embodiments, an optical device metrology system is configured to measure a plurality of first metrics and one or more second metrics for optical devices, the one or more second metrics including a display leakage metric.

Abstract: Disclosed herein are embodiments of a sensor device, systems incorporating the same, and methods of fabricating the same. In one embodiment, a sensor device comprises a free-standing sensing element, such as a micro-electromechanical system (MEMS) device. The sensor device further comprises a metallic band to facilitate mounting the MEMS device to a mounting plate. The sensor device further comprises a conformal coating on a least a portion of a sensor region of the sensor device.