Abstract: There is provided a system and method of runtime examination of a semiconductor specimen. The method includes obtaining a runtime image representative of an inspection area of the specimen, the runtime image having a relatively low signal-to-noise ratio (SNR); and processing the runtime image using a machine learning (ML) model to obtain examination data specific for a given examination application, wherein the ML model is previously trained for the given examination application using one or more training samples, each training sample representative of a respective reference area sharing the same design pattern as the inspection area and comprising: a first training image of the respective reference area having a relatively low SNR; and label data indicative of ground truth in the respective reference area pertaining to the given examination application, the label data obtained by annotating a second training image of the respective reference area having a relatively high SNR.

Abstract: A method of selectively and conformally doping semiconductor materials is disclosed. Some embodiments utilize a conformal dopant film deposited selectively on semiconductor materials by thermal decomposition. Some embodiments relate to doping non-line of sight surfaces. Some embodiments relate to methods for forming a highly doped crystalline semiconductor layer.

Abstract: A transistor device includes a channel region, a first source/drain region adjacent to a first end of the channel region and a second source/drain region adjacent to a second end of the channel region, a gate structure disposed on the channel region, the first source/drain region and the second source/drain region, and an interlayer dielectric (ILD) structure disposed on the gate structure. The ILD structure includes a first dielectric layer including a first set of sublayers. The first set of sublayers includes a first sublayer including a first dielectric material having a first hydrogen concentration and a second sublayer including the first dielectric material having a second hydrogen concentration lower than the first hydrogen concentration. The ILD structure further includes a second dielectric layer including a second set of sublayers. The second set of sublayers includes a third sublayer including a second dielectric material different from the first dielectric material.

Abstract: A polishing pad for a chemical mechanical polishing apparatus includes a polishing layer having a polishing surface and a backing layer formed of a fluid-permeable material. The backing layer includes a lower surface configured to be secured to a platen and an upper surface secured to the polishing layer, wherein the lower surface and upper surface are sealed. A first seal circumferentially seals an edge of the backing layer, and a second seal seals and separates the backing layer into a first region and a second region surrounded by the first region.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for semiconductor processing, more particularly, to a thermal process chamber. In one or more embodiments, a process chamber comprises a first window, a second window, a substrate support disposed between the first window and the second window, and a motorized rotatable radiant spot heating source disposed over the first window and configured to provide radiant energy through the first window.

Abstract: Embodiments provided herein generally include apparatus, plasma processing systems and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. One embodiment includes a waveform generator having a voltage source circuitry, a first switch coupled between the voltage source circuitry and a first output node of the waveform generator, the first output node being configured to be coupled to a chamber, and a second switch coupled between the first output node and electrical ground node. The waveform generator also includes a third switch coupled between the voltage source circuitry and a second output node of the waveform generator, the second output node being configured to be coupled to the chamber, and a fourth switch coupled between the second output node and the electrical ground node.

Abstract: Methods of semiconductor processing may include providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A feature may extend through one or more layers of material disposed on the substrate. The methods may include forming plasma effluents of the silicon-containing precursor and the oxygen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the silicon-containing precursor and the oxygen-containing precursor. The contacting may form a silicon-and-oxygen-containing material on at least a bottom portion of the feature. A temperature in the processing region may be maintained at less than or about 0° C.

Abstract: Variable orifice valves comprising a first fixed plate, a second fixed plate and a movable plate between are described. The movable plate is connected to the first fixed plate and the second fixed plate by sealing elements. The movable plate is moved closer to or further from the first fixed plate by rotation of an actuator ring that rotates at least two rotary elements connected to the movable plate. A needle on the movable plate engages an opening in the valve to seal or open the valve to allow fluid flow. Methods of controlling flow of fluid through the variable orifice valve are also described.

Abstract: Exemplary methods for a coating a component of a semiconductor processing system may include forming a nickel-containing alloy on an exposed surface the component of the semiconductor processing system. The methods may include forming plasma effluents of a fluorine-containing precursor. The methods may include contacting the nickel-containing alloy with the plasma effluents of the fluorine-containing precursor. The contacting may fluorinate a portion of the nickel-containing alloy to form a nickel-and-fluorine-containing material overlying the nickel-containing alloy.

Abstract: Exemplary semiconductor processing methods may include providing a boron-and-halogen-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A layer of metal-containing hardmask material may be disposed on the substrate. A layer of silicon-containing material may be disposed on the layer of metal-containing hardmask material. The methods may include forming plasma effluents of the boron-and-halogen-containing precursor and the oxygen-containing precursor. The methods may include contacting the substrate with the plasma effluents of the boron-and-halogen-containing precursor and the oxygen-containing precursor. The contacting may etch a feature in the layer of metal-containing hardmask material. The contacting may form a layer of passivation material on sidewalls of the feature in the layer of metal-containing hardmask material.

Abstract: An ion implanter may include an ion source to generate an ion beam. The ion implanter may include a set of beamline components to direct the ion beam to a substrate along a beam axis, as well as a process chamber to house the substrate to receive the ion beam. The ion implanter may include a conoscopy system, comprising: an illumination source to direct light to a substrate position; a first polarizer, having a first polarization axis, disposed between the illumination source and the substrate position; a second polarizer, the second polarizer being disposed to receive the light after passing through the substrate position. The conoscopy system may include a lens, to receive the light after passing through the substrate position, and a detector, to detect the light after passing through the lens.

Abstract: The present technology includes vertical cell array transistor (VCAT) that include a bit line arranged in a first horizontal direction and a word line arranged in a second horizontal direction. The arrays include a channel extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit line intersects with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the channels have at least one source/drain region and a channel body disposed between the first end and the second end. Arrays include where the channel body has a thickness that is greater than or about 5% less than a thickness of at least a portion of the at least one source/drain region.

Abstract: Exemplary seal cleaning apparatuses may include at least one support that is configured to receive a seal. The apparatuses may include a tool arm that is positionable within an interior of the seal. The apparatuses may include a pad holder that is rotatably coupled with the tool arm. The pad holder may include a body having a first end and a second end. The first end may define a channel that is configured to receive a cleaning pad. The body may define an aperture that extends from the second end through the channel. The pad holder may include a fluid fitting coupled with the aperture at the second end of the body. The apparatuses may include a cleaning fluid source that is fluidly coupled with the fluid fitting.

Abstract: An ion implanter, including an ion source generating an ion beam, a set of beamline components directing the ion beam to a substrate along a beam axis, normal to a reference plane, a process chamber housing the substrate to receive the ion beam, and a conoscopy system. The conoscopy system may include: an illumination source directing light to a substrate position, a first polarizer assembly, comprising a first polarizer element and first pair of lenses, disposed on opposite sides of the first polarizer element, and arranged to focus the light at the substrate position; a second polarizer assembly, disposed to receive the light after passing through the substrate position, including a second polarizer element and a second pair of lenses disposed on opposite sides of the second polarizer element, and arranged to focus the light at a sensor, disposed in a detector plane of a detector.

Abstract: Disclosed are method and system for calibrating a tilt angle of an electron beam of a backscattered scanning electron microscope including scanning a bare wafer at a plurality of electron beam tilt and azimuth angles, thereby obtaining a calibration map representing a crystal orientation of the bare wafer, selecting a tilt angle and defining an expected diffraction pattern associated with the tilt angle, based on the calibration map; scanning a patterned wafer at the selected tilt angle, comparing the diffraction pattern of the image obtained from the scanning of the patterned wafer at the selected tilt angle with the expected diffraction pattern; correcting the tilt angle of the electron beam of the BSEM tool, such that the diffraction pattern of the image obtained during scanning of the patterned wafer will align with the expected diffraction pattern.

Abstract: Electrochemical deposition systems and methods are described that have enhanced crystallization prevention features. The systems may include a bath vessel operable to hold an electrochemical deposition fluid having a metal salt dissolved in water. The systems may also include sensors including a thermometer and concentration sensor operable to measure characteristics of the electrochemical deposition fluid. The systems further include a computer configured to perform operations that include receiving system data from the electrochemical system and generating a control signal to change a characteristic of the electrochemical deposition fluid to prevent crystallization of a metal salt in the fluid. The computer generates the control signal based on processing that may include comparing an actual metal salt concentration in the electrochemical deposition fluid to a theoretical solubility limit for the metal salt in the fluid.

Abstract: Methods and systems for RF pulse monitoring and RF pulsing parameter optimization at a manufacturing system are provided. Sensor data is received from one or more sensors that indicates an RF pulse waveform detected within the processing chamber. One or more RF signal characteristics are identified in the detected RF pulse waveform. Each identified RF signal characteristic corresponds to at least one RF signal pulse of the RF signal pulsing within the processing chamber. A determination is made, based on the identified one or more RF signal characteristics, whether the detected RF pulse waveform corresponds to the target RF pulse waveform. An indication of whether the detected RF pulse waveform corresponds to the target RF pulse waveform is provided to a client device.

Abstract: A method for removing etchant byproduct from an etch reactor and discharging a substrate from an electrostatic chuck of the etch reactor is provided. One or more layers on a substrate electrostatically secured to an electrostatic chuck within a chamber of the etch reactor is etched using a first plasma, causing an etchant byproduct to be generated. A portion of the one or more layers are covered by a photoresist. After the etching is complete, a second plasma is provided into the chamber for a time period sufficient to trim the photoresist and remove a portion of the etchant byproduct. A second time period sufficient to electrostatically discharge the substrate using the second plasma is determined. Responsive to deactivating one or more chucking electrodes of the electrostatic chuck, the second plasma is provided into the chamber for the second time period and the substrate is removed from the chamber.

Abstract: Embodiments of the disclosure provided herein include a method for processing a substrate in a plasma processing system. The method includes receiving a first synchronization waveform signal from a controller, delivering a first burst of first voltage pulses to an electrode assembly after receiving a first portion of the first synchronization waveform signal, wherein at least one first parameter of the first voltage pulses is set to a first value based on a first waveform parameter within the first portion of the first synchronization waveform signal, and delivering a second burst of second voltage pulses to the electrode assembly after receiving a second portion of the first synchronization waveform signal, wherein the at least one first parameter of the first voltage pulses is set to a second value based on a difference in the first waveform parameter within the second portion of the first synchronization waveform signal.