Abstract: Systems, methods, and computer-readable mediums for monitoring temperature of a substrate are described. Spectroscopic measurements are performed on a surface of the substrate using a metrology tool integrated with a processing tool. The measurements may be used to determine that the substrate has cooled below a threshold temperature using the spectroscopic measurements.

Abstract: There is provided a method and a system configured to obtain metrology data Dmetrology informative of a plurality of structural parameters of a semiconductor specimen, obtain a model informative of a relationship between at least some of said structural parameters and one or more electrical properties of the specimen, use the model and Dmetrology to determine, for at least one given electrical property of the specimen, one or more given structural parameters among the plurality of structural parameters, which affect the given electrical property according to an impact criterion, and generate a recipe for an examination tool, wherein the recipe enables a ratio between a first acquisition rate of data informative of the one or more given structural parameters, and a second acquisition rate of data informative of other structural parameters of the plurality of structural parameters, to meet a criterion.

Abstract: Apparatus and methods to process one or more wafers are described. The apparatus comprises a chamber defining an upper interior region and a lower interior region. A heater assembly is on the bottom of the chamber body in the lower interior region and defines a process region. A wafer cassette assembly is inside the heater assembly and a motor is configured to move the wafer cassette assembly from the lower process region inside the heater assembly to the upper interior region.

Abstract: A method of processing an optical device is provided, including: positioning an optical device on a substrate support in an interior volume of a process chamber, the optical device including an optical device substrate and a plurality of optical device structures formed over the optical device substrate, each optical device structure including a bulk region formed of silicon carbide and one or more surface regions formed of silicon oxycarbide. The method further includes providing one or more process gases to the interior volume of the process chamber, and generating a plasma of the one or more process gases in the interior volume for a first time period when the optical device is on the substrate support, and stopping the plasma after the first time period. A carbon content of the one or more surface regions of each optical device structure is reduced by at least 50% by the plasma.

Abstract: A method of forming a semiconductor structure includes annealing a surface of a substrate in an ambient of hydrogen to smooth the surface, pre-cleaning the surface of the substrate, depositing a high-? dielectric layer on the pre-cleaned surface of the substrate, performing a re-oxidation process to thermally oxidize the surface of the substrate; performing a plasma nitridation process to insert nitrogen atoms in the deposited high-? dielectric layer, and performing a post-nitridation anneal process to passivate chemical bonds in the plasma nitridated high-? dielectric layer.

Abstract: A method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.

Abstract: A method of modifying an opening in a mask to achieve desired critical dimensions, the method including performing a pre-implant on the mask to implant the mask with a dopant material, wherein a material of the mask is densified and the opening is enlarged, directing a first radical beam at a first lateral side of the opening to deposit a layer of material on the first lateral side, and directing a second radical beam at a second lateral side of the opening opposite the first lateral side to deposit a layer of material on the second lateral side.

Abstract: A chiplet-based system may include a first chiplet mounted to an interposer that is designated as being from one or more trusted sources, a second chiplet mounted to the interposer that is designated as not being from the one or more trusted sources, and an artificial intelligence (AI) accelerator. The AI accelerator may be programmed to monitor a state of the first chiplet, where the state may indicate an anomaly associated with the second chiplet. The AI accelerator may then select an action from a plurality of actions based at least in part on the state of the first chiplet, cause the action to be performed by the chiplet-based system, and execute a reinforcement learning algorithm update the plurality of actions based on a result of the action being performed.

Abstract: Disclosed herein are methods for direct backside contact formation. In some embodiments, a method may include providing a stack of layers defining a front side and a backside, wherein the front side comprises one or more devices, and forming a plurality of vias in the backside, wherein each via of the plurality of vias extends to a source/drain. The method may further include performing a dopant implant to the backside including into the plurality of vias, wherein the dopant implant is performed at a temperature greater than 300° C., forming a silicide region within each of the source/drains, and forming a backside contact within each of the plurality of vias, wherein the backside contact is formed over the silicide region.

Abstract: Exemplary methods of packaging a substrate may include rotationally aligning a substrate to a predetermined angular position. The methods may include transferring the substrate to a metrology station. The methods may include measuring a topology of the substrate at the metrology station. The methods may include applying a first chucking force to the substrate to flatten the substrate. The methods may include generating a mapping of a die pattern on an exposed surface of the substrate. The methods may include transferring the substrate to a printing station. The methods may include applying a second chucking force to the substrate to flatten the substrate against a surface of the printing station. The methods may include adjusting a printing pattern based on the mapping of the die pattern. The methods may include printing the printing pattern on the exposed surface of the substrate.

Abstract: Vertical cell dynamic random-access memory (DRAM) arrays and methods of forming arrays with improved stability and word line resistivity are provided. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels. In addition, arrays include a bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, where the first channel is spaced apart from the second channel in a row extending in the second horizontal direction. Arrays include a gate formed around at least a portion of the plurality of channels and the bridge.

Abstract: A chemical mechanical polishing chamber may include a platen disposed within the chemical mechanical polishing chamber, the platen configured to support a polishing pad. The chamber may also include a slurry delivery arm configured to deliver a slurry to the polishing pad during a chemical mechanical polishing process. The chamber may include an arm may include one or more brackets, mechanically attached to an internal side of the chemical mechanical polishing chamber and positioned over the platen. The chamber may include a plurality of nozzles configured to deliver a gas to the polishing pad, the plurality of nozzles mechanically attached to the one or more brackets of the arm, each of the plurality of nozzles oriented such that an air gap is disposed between adjacent nozzles of the plurality of nozzles such that air may be pulled from the air gap and propelled with the gas towards the polishing pad.

Abstract: A first structure for semiconductor devices having a dielectric film on the top surface can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. The top surface of the dielectric film of the first structure can be hybrid bonded to a dielectric layer of a second structure. The dielectric film of the first structure and the dielectric layer of the second structure can be different dielectrics. In this way, the hybrid bonding of the two structures includes the hybrid bonding of asymmetric dielectrics.

Abstract: A substrate alignment system that includes (i) an illumination unit that is configured to illuminate an illuminated region that comprises an entire edge of a substrate; (ii) a sensing unit having a field of view that covers the entire edge of the substrate even when the substrate is misaligned, the sensing unit includes a sensor that is preceded by a fish eye lens, the sensor is configured to generate detection signals of the entire edge of the substrate; and (iii) a processing circuit that is configured to process the detection signals and determine whether the substrate is misaligned. A determining that the substrate is misaligned triggers an execution of one or more misalignment correction operation for aligning the substrate.

Abstract: A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface of the structure can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. For example, the dielectric constant of the dielectric film can be about or greater than 7 or 8. A semiconductor device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A dielectric film-oxide-metal-substrate structure can be formed with the dielectric film on the top surface of the stack. A multi-material etch can be used etch features in the dielectric film and the oxide in a dielectric film-oxide-metal-substrate stack. A chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.

Abstract: A structure for semiconductor devices having a high-dielectric constant dielectric film on the top surface can be used to form devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. The dielectric constant of the dielectric film can be about or greater than 8. A device can be formed by hybrid bonding the dielectric film of the structure to a dielectric film of a similar structure. A technique for forming the structure can include selectively depositing the dielectric film via atomic layer deposition after features filled with metal in a top layer of oxide in an oxide-metal-substrate stack. In order to selectively deposit the dielectric film, the metal may be covered with a polymer which can be burned off. A chemical-mechanical polishing technique can be used to precisely form the surface of the structure in preparation for hybrid bonding.

Abstract: Devices and methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.

Abstract: Methods of manufacturing electronic devices, such as transistors (negative metal-oxide-semiconductor (NMOS) transistors (e.g., an N-metal stack) and positive metal-oxide-semiconductor (PMOS) transistors (e.g., a P-metal stack)) are described. Embodiments of the disclosure are directed to methods of improving PMOS transistor performance by inhibiting N-metal layer growth. The present disclosure provides two types of processes to reduce or inhibit N-metal layer growth. The disclosure provides methods which include forming a self-assembled monolayer (SAM) on the metal surface (e.g., titanium nitride (TiN)) of the PMOS, and methods which include forming a silicon-containing layer such as silicon oxide (SiOx) on the TiN surface. These two types of processes significantly reduce or inhibit the subsequent growth of an N-metal layer, such as titanium aluminum carbide (TiAlC), on the TiN surface of the PMOS.