Abstract: The disclosure describes devices, systems and methods relating to a transfer chamber for an electronic device processing system. For example, a method includes causing a robot arm to pick up a substrate. The robot arm is caused to pick up the substrate by causing a first mover to rotate or to change a first distance to a second mover. Rotation of the first mover or the change in the first distance causes the first robot arm to rotate about a shoulder axis. The robot arm is further caused to pick up the substrate by causing one of a) a second mover to rotate or b) a third mover to change a second distance to the second mover. Rotation of the second mover or the change in the second distance causes the robot arm to raise or lower.

Abstract: The present disclosure is directed towards polishing modules for performing chemical mechanical polishing of a substrate. The substrate may be a semiconductor substrate. The polishing modules described have a plurality of pads, such as polishing pads, disposed within a single polishing station. The pads are configured to remain stationary during processing, such as during polishing or buff operations. Either an x-y gantry assembly or a head actuation assembly is coupled to a system body of a polishing module and is configured to move a carrier head over the pads. Between process operations the polishing pads may be indexed to expose a new polishing pad to the carrier head.

Abstract: Methods for monitoring process chambers using a controllable plasma oxidation process followed by a controlled reduction process and metrology are described. In some embodiments, the metrology comprises measuring the reflectivity of the metal oxide film formed by the controllable plasma oxidation process and the reduced metal film or surface modified film formed by reducing the metal oxide film.

Abstract: Disclosed are approaches for forming semiconductor device layers. One method may include forming a plurality of openings in a semiconductor structure, and forming a film layer atop the semiconductor structure by delivering a material at a non-zero angle relative to a normal extending perpendicular from an upper surface of the semiconductor structure. The film layer may be formed along the upper surface of the semiconductor structure without being formed along a sidewall of each opening of the plurality of openings, wherein an opening though the film layer remains above each opening of the plurality of openings.

Abstract: Electronic device manufacturing systems, robot apparatus and associated methods are described. The robot apparatus includes an arm having an inboard end and an outboard end, the inboard end is configured to rotate about a shoulder axis; a first forearm is configured for independent rotation relative to the arm about an elbow axis at the outboard end of the arm; a first wrist member is configured for independent rotation relative the first forearm about a first wrist axis at a distal end of the first forearm opposite the elbow axis, wherein the first wrist member includes a first end effector and a second end effector. The robot apparatus further includes a second forearm configured for independent rotation relative to the arm about the elbow axis; a second wrist member configured for independent rotation relative the second forearm about a second wrist axis, wherein the second wrist member comprises a third end effector and a fourth end effector.

Abstract: Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.

Abstract: A method for improving a quality of a secondary electron image of a region of a sample, the method may include obtaining a backscattered electron (BSE) image of the region and a secondary electron (SE) image of the region; wherein the BSE image and the SE image are generated by scanning of the region with an electron beam; processing the BSE image and the SE image to provide a processed BSE image and a processed SE image; and generating a BSE compensated SE image, wherein the generating comprises applying one or more selected BSE correction factors on one or more parts of the processed BSE image.

Abstract: Exemplary semiconductor processing systems may include a pumping system, a chamber body that defines a processing region, and a pumping liner disposed within the processing region. The pumping liner may define an annular member characterized by a wall that defines an exhaust aperture coupled to the pumping system. The annular member may be characterized by an inner wall that defines a plurality of apertures distributed circumferentially along the inner wall. A plenum may be defined in the annular member between interior surfaces of the walls. A divider may be disposed within the plenum, where the divider separates the plenum into a first plenum chamber and a second plenum chamber, wherein the first plenum chamber is fluidly accessible from the apertures defined through the inner wall, and wherein the divider defines at least one aperture providing fluid access between the first plenum chamber and the second plenum chamber.

Abstract: Methods of depositing improved quality silicon nitride (SixNy) films are disclosed. Exemplary methods include exposing a semiconductor substrate in a semiconductor processing chamber to a silicon-containing precursor, to a first plasma produced from a first gas mixture comprising helium (He) and nitrogen (N2), the first gas mixture comprising a ratio of helium:nitrogen in a range of from 20:1 to 1000:1, and exposing the semiconductor substrate to a second plasma produced from a second gas mixture comprising helium (He), nitrogen (N2), and ammonia (NH3).

Abstract: The interconnect resistances in a hybrid bonded structure can be controlled and designed. The resistance of each interconnect can be controlled by the width of the vias, the number of vias, and the thickness of liners within the vias. A first interconnect and a second interconnect of a hybrid bonded structure can have different interconnect resistances despite being on the same wafer or chip. The techniques described herein include designing interconnects and forming interconnects with particular resistances.

Abstract: Exemplary semiconductor processing methods may include flowing an etchant precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may define an exposed region of a metal-containing hardmask material and an exposed region of a material characterized by a dielectric constant of less than or about 4.0. The methods may include contacting the substrate with the etchant precursor. The methods may include removing at least a portion of the metal-containing hardmask material.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular, and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers that are protected from material loss during removal of a middle sacrificial layer. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a middle sacrificial layer on a top surface of the first hGAA structure, the middle sacrificial layer comprising silicon germanium (SiGe); and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise silicon germanium (SiGe).

Abstract: Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. Some embodiments of the methods include conventional dipole engineering techniques such as dipole first processes and/or dipole last processes without the need for repairing the interfacial layer after treatment (in dipole first processes) or repairing the high-? dielectric layer after the annealing process (in dipole last processes).

Abstract: A support unit for supporting a supported element, including (a) a spherical joint, (b) a pressure applying unit that is configured to maintain contact between a spherical outer surface and a base, (c) a position control unit that is configured to contact the spherical joint positioning element at multiple contact points and to set values of a first angle of rotation and a second angle of rotation of the spherical outer surface. The spherical joint is located above the position control unit. A distance between a fixed center of rotation and a point on the spherical outer surface is smaller than (b) a distance between the fixed center of rotation and any contact point of the multiple contact points.

Abstract: Embodiments of the present disclosure generally relate to methods of forming a substrate having a target thickness distribution at one or more eyepiece areas across a substrate. The substrate includes eyepiece areas corresponding to areas where optical device eyepieces are to be formed on the substrate. Each eyepiece area includes a target thickness distribution. A base substrate thickness distribution of a base substrate is measured such that a target thickness change can be determined. The methods described herein are utilized along with the target thickness change to form a substrate with the target thickness distribution.

Abstract: A method of cleaning a chamber for an electronics manufacturing system includes flowing a gas mixture comprising oxygen and a carrier gas into a remote plasma generator. The method further includes generating a plasma from the gas mixture by the remote plasma generator and performing a remote plasma cleaning of the chamber by flowing the plasma into an interior of the chamber, wherein the plasma removes a plurality of organic contaminants from the chamber.

Abstract: Embodiments of the present disclosure relate to methods for forming a source/drain extension. In one embodiment, a method for forming an nMOS device includes forming a gate electrode and a gate spacer over a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to expose a side wall and a bottom, forming a silicon arsenide (Si:As) layer on the side wall and the bottom, and forming a source/drain region on the Si:As layer. During the deposition of the Si:As layer and the formation of the source/drain region, the arsenic dopant diffuses from the Si:As layer into a third portion of the semiconductor fin located below the gate spacer, and the third portion becomes a doped source/drain extension region. By utilizing the Si:As layer, the doping of the source/drain extension region is controlled, leading to reduced contact resistance while reducing dopants diffusing into the channel region.

Abstract: A method of operating a beamline ion implanter may include performing, in an ion implanter, a first implant procedure to implant a dopant of a first polarity into a given semiconductor substrate, and generating an estimated implant dose of the dopant of the first polarity based upon a set of filtered information, generated by the first implant procedure. The method may also include calculating an actual implant dose of the dopant of the first polarity using a predictive model based upon the estimated implant dose, and performing, in the ion implanter, an adjusted second implant procedure to implant a dopant of a second polarity into a select semiconductor substrate, based upon the actual implant dose.

Abstract: Provided herein are approaches for providing a more uniform ion flux and ion angular distribution across a wafer to minimize etch yield loss resulting from etch profile variations. In some embodiments, a system may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, wherein the plasma source comprises a plasma shaper extending into the plasma chamber from a wall of the chamber housing. The plasma shaper may include a shaper wall coupled to the wall of the chamber housing, and a shaper end wall connected to the shaper wall, the shaper end wall defining an indentation extending towards the wall of the chamber housing.

Abstract: Embodiments of the present disclosure relate to a system, a software application, and a method of a lithography process to update one or more of a mask pattern, maskless lithography device parameters, lithography process parameters utilizing a file readable by each of the components of a lithography environment. The file readable by each of the components of a lithography environment stores and shares textual data and facilitates communication between of the components of a lithography environment such that the mask pattern corresponds to a pattern to be written is updated, the maskless lithography device of the lithography environment is calibrated, and process parameters of the lithography process are corrected for accurate writing of the mask pattern on successive substrates.