Abstract: Inspection data that corresponds to potential defects of an object may be received. A first set of locations of first potential defects can be identified. The first set of locations of the first potential defects can be imaged with a review tool to obtain a first set of review images. The first potential defects can be classified based on the first set of review images to obtain first classification results of the first potential defects. An instruction can be determined for the review tool based on the first classification results, the instruction being associated with detecting potential defects. Using the instruction, a second set of locations of second potential defects of the plurality of potential defects to be imaged with the review tool can be identified.

Abstract: Exemplary substrate processing systems may include a transfer region housing defining a transfer region fluidly coupled with a plurality of processing regions. A sidewall of the transfer region housing may define a sealable access for providing and receiving substrates. The systems may include a transfer apparatus having a central hub including a shaft extending at a distal end through the transfer region housing into the transfer region. The transfer apparatus may include a lateral translation apparatus coupled with an exterior surface of the transfer region housing, and configured to provide at least one direction of lateral movement of the shaft. The systems may also include an end effector coupled with the shaft within the transfer region. The end effector may include a plurality of arms having a number of arms equal to a number of substrate supports of the plurality of substrate supports in the transfer region.

Abstract: Exemplary semiconductor processing chamber showerheads may include a dielectric plate characterized by a first surface and a second surface opposite the first surface. The dielectric plate may define a plurality of apertures through the dielectric plate. The dielectric plate may define a first annular channel in the first surface of the dielectric plate, and the first annular channel may extend about the plurality of apertures. The dielectric plate may define a second annular channel in the first surface of the dielectric plate. The second annular channel may be formed radially outward from the first annular channel. The showerheads may also include a conductive material embedded within the dielectric plate and extending about the plurality of apertures without being exposed by the apertures. The conductive material may be exposed at the second annular channel.

Abstract: The present disclosure relates to a support ring for a thermal processing chamber. The support ring has a polysilicon coating. The polysilicon coating is formed using a plasma spray deposition process.

Abstract: The present disclosure generally relates to methods and systems for manufacturing wire grid polarizers (WGP) using Markle-Dyson exposure systems and dual tone development (DTD) frequency doubling. In one embodiment, the method includes depositing a photoresist layer over an aluminum-coated display substrate, patterning the photoresist layer by dual tone development using a Markle-Dyson system to form a photoresist pattern, and transferring the photoresist pattern into the aluminum-coated display substrate to manufacture a WGP having finer pitch, for example less than or equal to about 100 nm, and increased frequency.

Abstract: A method of modifying a high-resistivity substrate so that the substrate may be electrostatically clamped to a chuck is disclosed. The bottom surface is implanted with a resistivity-reducing species. In this way, resistivity of the bottom surface of the substrate may be greatly reduced. In some embodiments, to implant the bottom surface, a coating is applied to the top surface. After application of the coating, the substrate is flipped so that the front surface contacts the top surface of the chuck. The ions are then implanted into the exposed bottom surface to create the low resistivity layer. The resistivity of the low resistivity layer proximate the bottom surface after implant may be less than 1000 ohm-cm. Once the bottom surface has been implanted, the substrate may be processed conventionally. The low resistivity layer may later be removed by wafer backside thinning processes.

Abstract: Exemplary methods of forming a silicon-and-carbon-containing material may include flowing a silicon-and-carbon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the silicon-and-carbon-containing precursor. The plasma may be formed at a frequency above 15 MHz. The methods may include depositing a silicon-and-carbon-containing material on the substrate. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant below or about 3.0.

Abstract: Described are memory devices having stacked DRAM cells, resulting in an increase in DRAM cell bit-density. The area of a unit cell is composed of a capacitor, a cell transistor, an isolation region and a connection region, where every capacitor and active region for the cell capacitor is electrically isolated. The memory cells have supporting bars. Methods of forming a memory device are described. The methods include patterning the isolation region with supporting bars, removing non-insulator layers after isolation region patterning, and filling the opened region with an insulator.

Abstract: Exemplary methods of semiconductor processing may include forming a layer of carbon-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The substrate may include an exposed region of a first dielectric material and an exposed region of a metal-containing material. The layer of carbon-containing material may be selectively formed over the exposed region of the metal-containing material. Forming the layer of carbon-containing material may include one or more cycles of providing a first molecular species that selectively couples with the metal-containing material. Forming the layer of carbon-containing material may include providing a second molecular species that selectively couples with the first molecular species. The methods may include selectively depositing a second dielectric material on the exposed region of the first dielectric material.

Abstract: Exemplary methods of semiconductor processing may include etching one or more features partially through a stack of layers formed on a substrate. The methods may include halting the etching prior to penetrating fully through the stack of layers formed on the substrate. The methods may include forming a layer of carbon-containing material along the stack of layers on the substrate. The layer of carbon-containing material may include a metal. The methods may include etching the one or more features fully through the stack of layers on the substrate.

Abstract: An adjustable attenuation optical unit that may include a lightguide that includes a core, wherein the core comprises an output, an input and an exterior surface; and an adjustable attenuator that is configured to define an interfacing parameter related to an area of the exterior surface thereby receiving at least some of the light that impinges on the area.

Abstract: Pedestal assemblies, purge rings for pedestal assemblies, and processing methods for increasing residence time of an edge purge gas in heated pedestal assemblies are described. Purge rings have an inner diameter face and an outer diameter face defining a thickness of the purge ring, a top surface and a bottom surface defining a height of the purge ring, and a thermal expansion feature. Purge rings comprise a plurality of apertures extending through the thickness and aligned circumferentially with a plurality of circumferentially spaced purge outlets in a substrate support.

Abstract: Exemplary slurry delivery assemblies may include a slurry fluid source. The assemblies may include a flurry delivery lumen having a lumen inlet and a lumen outlet. The lumen inlet may be fluidly coupled with an output of the slurry fluid source. The assemblies may include a deagglomeration tube fluidly coupled with the lumen outlet. The deagglomeration tube may include a tube inlet and a tube outlet. The assemblies may include one or more ultrasonic transducers coupled with the deagglomeration tube.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The methods form a 3D DRAM architecture that includes a semiconductor isolation bridge, eliminating a floating body effect. The method includes forming an epitaxial layer in a deep trench isolation opening and creating a semiconductor isolation bridge between adjacent deep trench isolation openings.

Abstract: A method includes receiving a spot beam profile is received for a spot ion beam; receiving a linear scanned beam profile for the spot ion beam; generating a calculated calibration spot profile, based upon the spot beam profile and the linear scanned beam profile; and implementing an adjusted scanned profile for the spot ion beam, based upon the calculated calibration spot profile.

Abstract: Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.

Abstract: Analyzing a sidewall of a hole milled in a sample to determine thickness of a buried layer includes milling the hole in the sample using a charged particle beam of a focused ion beam (FIB) column to expose the buried layer along the sidewall of the hole. After milling, the sidewall of the hole has a known slope angle. From a perspective relative to a surface of the sample, a distance is measured between a first point on the sidewall corresponding to an upper surface of the buried layer and a second point on the sidewall corresponding to a lower surface of the buried layer. The thickness of the buried layer is determined using the known slope angle of the sidewall, the distance, and the angle relative to the surface of the sample.

Abstract: Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a lid plate seated on the chamber body. The lid plate may define a plurality of apertures. The systems may include a plurality of lid stacks equal to a number of the plurality of apertures. The systems may include a plurality of substrate support assemblies equal to the number of apertures defined through the lid plate. Each assembly may be disposed in one of the processing regions and may include an electrostatic chuck body defining a substrate support surface that defines a substrate seat. Each assembly may include a heater embedded within the chuck body. Each assembly may include bipolar electrodes between the heater and the substrate support surface. Each assembly may include a conductive mesh embedded within the body between the heater and bipolar electrodes.

Abstract: A ferroelectric tunnel junction (FTJ) memory device may include a first electrode and a ferroelectric layer comprising ferroelectric dipoles that may generate a first electric field. The first electric field may be oriented in a first direction when the device operates in an ON state. The device may also include a barrier layer that may generate a depolarizing second electric field that may be oriented in a second direction opposite of the first direction when the device operates in the ON state. The device may further include a second electrode. The first electrode and the second electrode may generate a third electric field that is oriented in the first direction when the device operates in the ON state.

Abstract: A method of correcting bias temperature instability in memory arrays may include applying a first bias to a memory cell, where the memory cell may include a memory element and a select element, and the first bias may causes a value to be stored in the memory element. The first bias causes a bias temperature instability (BTI) associated with the memory cell to increase. The method may also include applying a second bias to the memory cell, where the second bias may have a polarity that is opposite of the first bias, and the value stored in the memory element remains in the memory element after the second bias is applied. The second bias may also cause the BTI associated with the memory cell to decrease while maintaining any value stored in the memory cell.