Abstract: Exemplary methods of electroplating may include providing a patterned substrate having at least one opening, where the opening includes one or more sidewalls and a bottom surface. The methods may also include plating a first portion of ruthenium-containing material on the bottom surface of the opening at a first deposition rate and a second portion of ruthenium-containing material on the sidewalls of the opening at a second deposition rate, where the first deposition rate is greater than the second deposition rate. The methods may be used to make integrated circuit devices that include void-free, electrically-conductive lines and columns of ruthenium-containing materials.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

Abstract: Exemplary methods of electroplating include contacting a patterned substrate with a plating bath in an electroplating chamber, where the pattern substrate includes at least one opening having a bottom surface and one or more sidewall surfaces. The methods may further include forming a nanotwin-containing metal material in the at least one opening. The metal material may be formed by two or more cycles that include delivering a forward current from a power supply through the plating bath of the electroplating chamber for a first period of time, plating a first amount of the metal on the bottom surface of the opening on the patterned substrate and a second amount of the metal on the sidewall surfaces of the opening, and delivering a reverse current from the power supply through the plating bath of the electroplating chamber to remove some of the metal plated in the opening on the patterned substrate.

Abstract: Exemplary methods of electroplating a metal with a nanotwin crystal structure are described. The methods may include plating a metal material into at least one opening on a patterned substrate, where at least a portion of the metal material is characterized by a nanotwin crystal structure. The methods may further include polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm. The polished exposed surface may include at least a portion of the metal material characterized by the nanotwin crystal structure. In additional examples, the nanotwin-phased metal may be nanotwin-phased copper.

Abstract: Exemplary methods of manufacturing a semiconductor cover wafer may include sintering aluminum nitride particles into a substrate characterized by a thickness and characterized by a disc shape. The methods may include grinding a surface of the substrate to reduce the thickness to less than or about 2 mm. The methods may include polishing the surface of the substrate to reduce a roughness. The methods may include annealing the substrate at a temperature of greater than or about 800° C. for a time period of greater than or about 60 minutes.

Abstract: Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.

Abstract: Methods for plasma enhanced chemical vapor deposition (PECVD) of silicon carbonitride films are described. A flowable silicon carbonitride film is formed on a substrate surface by exposing the substrate surface to a precursor and a reactant, the precursor having a structure of general formula (I) or general formula (II) wherein R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, and R12 are independently selected from hydrogen (H), substituted or unsubstituted alkyl, substituted or unsubstituted alkoxy, substituted or unsubstituted vinyl, silane, substituted or unsubstituted amine, or halide; purging the processing chamber of the silicon precursor, and then exposing the substrate to an ammonia plasma.

Abstract: Extreme ultraviolet (EUV) mask blanks, production systems therefor, and methods of increasing multilayer film reflectance are disclosed. The EUV mask blanks comprise a bilayer film on a substrate. The bilayer film comprises a first film layer including silicon (Si), and a second film layer comprising an element selected from the group consisting of ruthenium (Ru), nickel (Ni), cobalt (Co), tungsten (W), iron (Fe), titanium (Ti) and silicides thereof. Some EUV mask blanks further comprise a multilayer reflective stack comprising alternating layers on the bilayer film and a capping layer on the multilayer reflective stack. Some EUV mask blanks include a smoothing layer selected from the group consisting of molybdenum silicide (MoSi), boron carbide (B4C) and silicon nitride (SiN) on the multilayer reflective stack, a capping layer on the smoothing layer, and an absorber layer on the capping layer.

Abstract: Exemplary methods of semiconductor processing may include forming a plasma of a carbon-containing precursor in a processing region of a semiconductor processing chamber. The methods may include depositing a carbon-containing material on a substrate housed in the processing region of the semiconductor processing chamber. The methods may include halting a flow of the carbon-containing precursor into the processing region of the semiconductor processing chamber. The methods may include contacting the carbon-containing material with plasma effluents of an oxidizing material. The methods may include forming volatile materials from a surface of the carbon-containing material.

Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.

Abstract: Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, with growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

Abstract: A method reduces differences in chucking forces that are applied by two electrodes of an electrostatic chuck, to a substrate disposed atop the chuck. The method includes providing initial chucking voltages to each of the two electrodes, and measuring an initial current provided to at least a first electrode of the two electrodes. The method further includes initiating a process that affects a DC voltage of the substrate, then measuring a modified current provided to at least the first electrode, and determining, based at least on the initial current and the modified current, a modified chucking voltage for a selected one of the two electrodes, that will reduce chucking force imbalance across the substrate. The method also includes providing the modified chucking voltage to the selected one of the two electrodes.

Abstract: A wafer chuck assembly includes a puck, a shaft and a base. The puck includes an electrically insulating material that defines a top surface of the puck; a plurality of electrodes are embedded within the electrically insulating material. The puck also includes an inner puck element that forms one or more channels for a heat exchange fluid, the inner puck element being in thermal communication with the electrically insulating material, and an electrically conductive plate disposed proximate to the inner puck element. The shaft includes an electrically conductive shaft housing that is electrically coupled with the plate, and a plurality of connectors, including electrical connectors for the electrodes. The base includes an electrically conductive base housing that is electrically coupled with the shaft housing, and an electrically insulating terminal block disposed within the base housing, the plurality of connectors passing through the terminal block.

Abstract: Methods, systems, and non-transitory computer readable medium are described for sensor metrology data integration. A method includes receiving sets of sensor data and sets of metrology data. Each set of sensor data includes corresponding sensor values associated with producing corresponding product by manufacturing equipment and a corresponding sensor data identifier. Each set of metrology data includes corresponding metrology values associated with the corresponding product manufactured by the manufacturing equipment and a corresponding metrology data identifier. The method further includes determining common portions between each corresponding sensor data identifier and each corresponding metrology data identifier. The method further includes, for each of the sensor-metrology matches, generating a corresponding set of aggregated sensor-metrology data and storing the sets of aggregated sensor-metrology data to train a machine learning model.

Abstract: One embodiment of the disclosure provides a method of fabricating a chamber component with a coating layer disposed on an interface layer with desired film properties. In one embodiment, a method of fabricating a coating material includes providing a base structure comprising an aluminum or silicon containing material, forming an interface layer on the base structure, wherein the interface layer comprises one or more elements from at least one of Ta, Al, Si, Mg, Y, or combinations thereof, and forming a coating layer on the interface layer, wherein the coating layer has a molecular structure of SivYwMgxAlyOz. In another embodiment, a chamber component includes an interface layer disposed on a base structure, wherein the interface layer is selected from at least one of Ta, Al, Si, Mg, Y, or combinations thereof, and a coating layer disposed on the interface layer, wherein the coating layer has a molecular structure of SivYwMgxAlyOz.

Abstract: Methods to manufacture integrated circuits are described. Nanocrystalline diamond is used as a hard mask in place of amorphous carbon. Provided is a method of processing a substrate in which nanocrystalline diamond is used as a hard mask, wherein processing methods result in a smooth surface. The method involves two processing parts. Two separate nanocrystalline diamond recipes are combined—the first and second recipes are cycled to achieve a nanocrystalline diamond hard mask having high hardness, high modulus, and a smooth surface. In other embodiments, the first recipe is followed by an inert gas plasma smoothening process and then the first recipe is cycled to achieve a high hardness, a high modulus, and a smooth surface.

Abstract: Methods of forming a tungsten film comprising forming a boron seed layer on an oxide surface, an optional tungsten initiation layer on the boron seed layer and a tungsten containing film on the boron seed layer or tungsten initiation layer are described. Film stack comprising a boron seed layer on an oxide surface with an optional tungsten initiation layer and a tungsten containing film are also described.

Abstract: An apparatus may include a drift tube assembly, arranged to transmit an ion beam. The drift tube assembly may include a first ground electrode; an RF drift tube assembly, disposed downstream of the first ground electrode; and a second ground electrode, disposed downstream of the RF drift tube assembly. The RF drift tube assembly may define a triple gap configuration. The apparatus may include a resonator, where the resonator comprises a toroidal coil, having a first end, connected to a first RF drift tube of the RF drift tube assembly, and a second end, connected to a second RF drift tube of the RF drift tube assembly.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer comprising an alloy of molybdenum (Mo) and antimony (Sb).