Patents Assigned to Applied Material
  • Publication number: 20230040358
    Abstract: Methods may include providing a device structure having a shielding layer formed beneath each trench in a MOSFET to protect trench corner breakdown. The method may include providing a device structure comprising an epitaxial layer, a well over the epitaxial layer, and a source layer over the well, and providing a plurality of trenches through the device structure. The method may further include forming a shielding layer in the device structure by directing ions into the plurality of trenches.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Qintao Zhang, Samphy Hong
  • Publication number: 20230041405
    Abstract: A method of characterizing defects in semiconductor layers may include forming a first electrode, a first barrier layer, a semiconductor layer, and a second electrode, where the first barrier layer is between the first electrode and the semiconductor layer, and the semiconductor layer is between the first barrier layer and the second electrode. The method may also include causing current to flow through the semiconductor layer, where the first barrier layer prevents the current from entering a conduction band of the semiconductor layer and instead causes current to flow through defects in the semiconductor layer. The method may also include characterizing the defects in the semiconductor layer based on the current flowing through the defects in the semiconductor layer.
    Type: Application
    Filed: August 3, 2021
    Publication date: February 9, 2023
    Applicant: Applied Materials, Inc.
    Inventor: Milan Pesic
  • Publication number: 20230039074
    Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.
    Type: Application
    Filed: October 18, 2022
    Publication date: February 9, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Michael Stolfi, Myungsun Kim, Benjamin Colombeau, Sanjay Natarajan
  • Publication number: 20230037450
    Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.
    Type: Application
    Filed: October 18, 2022
    Publication date: February 9, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Sean M. Seutter, Mun Kyu Park, Hien M Le, Chih-Chiang Chuang
  • Publication number: 20230040606
    Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is crystallized. Epitaxially growth of the source and drain regions then proceeds, which growth advantageously occurring on the bottom and sidewalls of the source and drain regions.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 9, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Benjamin Colombeau, Saurabh Chopra, Myungsun Kim, Balasubramanian Pranatharthiharan
  • Patent number: 11574796
    Abstract: An aperture diaphragm capable of varying the size of an aperture in two dimensions is disclosed. The aperture diaphragm may be utilized in an ion implantation system, such as between the mass analyzer and the acceleration column. In this way, the aperture diaphragm may be used to control at least one parameter of the ion beam. These parameters may include angular spread in the height direction, angular spread in the width direction, beam current or cross-sectional area. Various embodiments of the aperture diaphragm are shown. In certain embodiments, the size of the aperture in the height and width directions may be independently controlled, while in other embodiments, the ratio between height and width is constant.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Jun Lu, Frank Sinclair, Shane W. Conley, Michael Honan
  • Patent number: 11574825
    Abstract: A method and apparatus for processing a semiconductor is disclosed herein. In one embodiment, a processing system for semiconductor processing is disclosed. The processing chamber includes two transfer chambers, a processing chamber, and a rotation module. The processing chamber is coupled to the transfer chamber. The rotation module is positioned between the transfer chambers. The rotation module is configured to rotate the substrate. The transfer chambers are configured to transfer the substrate between the processing chamber and the transfer chamber. In another embodiment, a method for processing a substrate on the apparatus is disclosed herein.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Tuan Anh Nguyen, Amit Kumar Bansal, Juan Carlos Rocha-Alvarez
  • Patent number: 11574831
    Abstract: Examples of the present invention provide an apparatus for transferring substrates and confining a processing environment in a chamber. One example provides a hoop assembly for use in a processing chamber. The hoop assembly includes a confinement ring defining a confinement region therein. A hoop body mates with the confinement ring. The hoop body is slanted to reduce a thickness across a diameter of the hoop body. Three or more lifting fingers are attached to the hoop body and extend downwards. Each of the three or more lifting fingers has a contact tip positioned radially inward from the hoop body to form a substrate support surface below and spaced apart from the confinement region.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Jared Ahmad Lee, Martin Jeffrey Salinas, Paul B. Reuter, Imad Yousif, Aniruddha Pal
  • Patent number: 11571786
    Abstract: A polishing apparatus includes a polishing station to hold a polishing pad, a carrier head to hold a substrate in contact with a polishing pad at the polishing station, a camera positioned to capture an image of a lower surface of a consumable part when the consumable part moves away from the polishing pad, and a controller configured to perform an image processing algorithm on the image to determine whether the consumable part is damaged. The consumable part can be a retaining ring on a carrier head, or a conditioner disk on a conditioner head.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Thomas H. Osterheld, Dominic J. Benvegnu
  • Patent number: 11572622
    Abstract: Exemplary semiconductor processing methods to clean a substrate processing chamber are described. The methods may include depositing a dielectric film on a first substrate in a substrate processing chamber, where the dielectric film may include a silicon-carbon-oxide. The first substrate having the dielectric film may be removed from the substrate processing chamber, and the dielectric film may be deposited on at least one more substrate in the substrate processing chamber. The at least one more substrate may be removed from the substrate processing chamber after the dielectric film is deposited on the substrate. Etch plasma effluents may flow into the substrate processing chamber after the removal of a last substrate having the dielectric film. The etch plasma effluents may include greater than or about 500 sccm of NF3 plasma effluents, and greater than or about 1000 sccm of O2 plasma effluents.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Bo Xie, Ruitong Xiong, Kang Sub Yim, Yijun Liu, Li-Qun Xia, Sure K. Ngo
  • Patent number: 11574826
    Abstract: Exemplary substrate processing systems may include a factory interface and a load lock coupled with the factory interface. The systems may include a transfer chamber coupled with the load lock. The transfer chamber may include a robot configured to retrieve substrates from the load lock. The systems may include a chamber system positioned adjacent and coupled with the transfer chamber. The chamber system may include a transfer region laterally accessible to the robot. The transfer region may include a plurality of substrate supports disposed about the transfer region. Each substrate support of the plurality of substrate supports may be vertically translatable. The transfer region may also include a transfer apparatus rotatable about a central axis and configured to engage substrates and transfer substrates among the plurality of substrate supports. The chamber system may also include a plurality of processing regions vertically offset and axially aligned with an associated substrate support.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Jason M. Schaller, Steve Hongkham, Charles T. Carlson, Tuan A. Nguyen, Swaminathan T. Srinivasan, Khokan Chandra Paul
  • Patent number: 11575065
    Abstract: A quantum device includes a substrate including a first material and including an upper surface thereof, a first layer comprising a compound of the first material disposed on the upper surface of the substrate, a second layer, comprising a metal oxide, disposed on the first layer, a third layer, comprising a noble metal, disposed on the second layer, a fourth layer, comprising a metal oxide, disposed on the third layer, a fifth layer, comprising a piezoelectric material, disposed on the fourth layer, a sixth layer, comprising a noble metal, disposed on the fifth layer, a seventh layer, comprising a material capable of quantum emission, disposed on the sixth layer, and an eighth layer, comprising a noble metal, disposed on the seventh layer, and at least one of the eighth layer and the seventh layer are sized to enable quantum emission from the seventh layer.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventor: Abhijeet Laxman Sangle
  • Patent number: 11574924
    Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure and a center filling layer, wherein the metal dielectric layer in the opening is interfaced with the conductive structure.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Changseok Kang, Tomohiko Kitajima
  • Patent number: 11576264
    Abstract: An electronic device manufacturing system includes a mainframe that includes a first transfer chamber and facets defining first side walls of the first transfer chamber. The facets include a first facet that has a first number of substrate access ports, a second facet that has a second number of substrate access ports, and a third facet that has the second number of substrate access ports. The second number of substrate access ports is different than the first number of substrate access ports.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Michael Robert Rice, Jeffrey C. Hudgens
  • Patent number: 11574950
    Abstract: A method of fabricating CMOS image sensors is disclosed. In contrast to traditional fabrication processes, the present sequence implants dopants into the epitaxial layer from both the first surface and the second surface. Because dopant is introduced through both sides, the maximum implant energy to perform the implant may be reduced by as much as 50%. In certain embodiments, the second implant is performed prior to the application of the electrical contacts. In another embodiments, the second implant is performed after the application of the electrical contacts. This method may allow deeper photodiodes to be fabricated using currently available semiconductor processing equipment than would otherwise be possible.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventor: Venkataramana R. Chavva
  • Patent number: 11576252
    Abstract: An apparatus may include global control module, the global control module including a digital master clock generator and a master waveform generator. The apparatus may also include a plurality of resonator control modules, coupled to the global control module. A given resonator control module of the plurality of resonator control modules may include a synchronization module, having a first input coupled to receive a resonator output voltage pickup signal from a local resonator, a second input coupled to receive a digital master clock signal from the digital master clock generator, and a first output coupled to send a delay signal to the master waveform generator.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventor: Keith E. Kowal
  • Patent number: 11572617
    Abstract: An article comprises a body having a protective coating. The protective coating is a thin film that comprises a metal oxy-fluoride. The metal oxy-fluoride has an empirical formula of MxOyFz, where M is a metal, y has a value of 0.1 to 1.9 times a value of x and z has a value of 0.1 to 3.9 times the value of x. The protective coating has a thickness of 1 to 30 microns and a porosity of less than 0.1%.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: David Fenwick, Chengtsin Lee, Jennifer Y. Sun, Yikai Chen
  • Patent number: 11575071
    Abstract: Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Mingwei Zhu, Nag B. Patibandla, Rongjun Wang, Daniel Lee Diehl, Vivek Agrawal, Anantha Subramani
  • Patent number: 11573452
    Abstract: Processing methods may be performed to forming a pixel material in a semiconductor structure. The methods may include forming a sacrificial hardmask overlying an uppermost layer of an optical stack of the semiconductor structure, the uppermost layer having a thickness. The methods may include forming a via through the sacrificial hardmask in the optical stack by a first etch process unselective to a metal layer of the semiconductor structure. The methods may include filling the via with a fill material, wherein a portion of the fill material extends over the sacrificial hardmask and contacts the metal layer. The methods may include removing a portion of the fill material external to the via by a removal process selective to the fill material. The methods may also include removing the sacrificial hardmask by a second etch process selective to the sacrificial hardmask while maintaining the thickness of the uppermost layer.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Lan Yu, Benjamin D. Briggs, Tyler Sherwood, Raghav Sreenivasan
  • Patent number: D977504
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Upendra V. Ummethala, Blake Erickson, Prashanth Kumar, Michael Kutney, Steven Trey Tindel, Zhaozhao Zhu