Abstract: Exemplary integrated cluster tools may include a factory interface including a first transfer robot. The tools may include a wet clean system coupled with the factory interface at a first side of the wet clean system. The tools may include a load lock chamber coupled with the wet clean system at a second side of the wet clean system opposite the first side of the wet clean system. The tools may include a first transfer chamber coupled with the load lock chamber. The first transfer chamber may include a second transfer robot. The tools may include a second transfer chamber coupled with the first transfer chamber. The second transfer chamber may include a third transfer robot. The tools may include a metal deposition chamber coupled with the transfer chamber.

Abstract: Methods of cleaning a substrate support comprise: introducing a cleaning gas into a processing chamber containing the substrate support; applying a radio frequency (RF) power to a remote plasma source that is in fluid communication with the processing chamber to establish a reactive etching plasma from the cleaning gas in the processing chamber; reacting deposits on the substrate support with the reactive etching plasma to form a by-products phase; and evacuating the by-products phase from the processing chamber.

Abstract: Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200° C. by using an organic platinum group metal precursor.

Abstract: Embodiments disclosed herein include methods of depositing a metal oxo photoresist using dry deposition processes. In an embodiment, the method comprises forming a first metal oxo film on the substrate with a first vapor phase process including a first metal precursor vapor and a first oxidant vapor, and forming a second metal oxo film over the first metal oxo film with a second vapor phase process including a second metal precursor vapor and a second oxidant vapor.

Abstract: Embodiments of the present disclosure generally relate to apparatus and methods utilized in the manufacture of semiconductor devices. More particularly, embodiments of the present disclosure relate to a substrate processing chamber, and components thereof, for forming semiconductor devices.

Abstract: The present invention relates to the field of coating pharmaceutical substrates. In particular, the invention relates to methods of coating of pharmaceutical substances, pharmaceutical ingredients or a blend of them. The invention also provides a method of making a pharmaceutical formulation which may be processed into a pharmaceutical dosage form, which utilizes solid pharmaceutical particles and a pharmaceutical formulation obtained by the method. The methods of the invention utilize atomic layer deposition technology. The novel methods allow difficult, moisture sensitive and electrically charged pharmaceutical substrates to be easily processable.

Abstract: Embodiments disclosed herein include a housing for a source assembly. In an embodiment, the housing comprises a conductive body with a first surface and a second surface opposite from the first surface, and a plurality of openings through a thickness of the conductive body between the first surface and the second surface. In an embodiment, the housing further comprises a channel into the first surface of the conductive body, and a cover over the channel. In an embodiment, a first stem over the cover extends away from the first surface, and a second stem over the cover extends away from the first surface. In an embodiment, the first stem and the second stem open into the channel.

Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region, and the substrate may be maintained at a temperature below or about 450° C. The methods may include striking a plasma of the silicon-containing precursor. The methods may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by less than or about 3% hydrogen incorporation.

Abstract: Methods, systems, and apparatus provide for optically monitoring individual lamps of substrate processing chambers. In one aspect, the individual lamps are monitored to determine if one or more lamps are in need of replacement. A method includes using one or more camera coupled to a borescope to capture a plurality of images of one or more lamps in a substrate processing chamber. The plurality of images is analyzed to identify a change of mean light pixel intensity in an image reference region associated with each lamp. The method includes generating an alert based on the detection of the mean light pixel intensity change.

Abstract: There is provided a system to examine a semiconductor specimen, the system comprising a processor and memory circuitry configured to obtain a training sample comprising an image of a semiconductor specimen and a design image based on design data, train a machine learning module, wherein the training includes minimizing a function representative of a difference between a simulated image generated by the machine learning module based on a given design image, and a corrected image corresponding to a given image after correction of pixel position of the given image in accordance with a given displacement matrix, wherein the minimizing includes optimizing parameters of the machine learning module and of the given displacement matrix, wherein the trained machine learning module is usable to generate a simulated image of a specimen based on a design image of the specimen.

Abstract: A beamline ion implanter and a method of operating a beamline ion implanter. A method may include performing an ion implantation procedure during a first time period on a first set of substrates, in a process chamber of the ion implanter, and performing a first pressure-control routine during a second time period by: introducing a predetermined gas to reach a predetermined pressure into at least a downstream portion of the beam-line for a second time period. The method may include, after completion of the first pressure-control routine, performing the ion implantation procedure on a second set of substrates during a third time period.

Abstract: A precursor delivery system is described herein. Some embodiments provide a precursor delivery system capable of providing a uniform gas flow comprising precursor into a processing chamber for atomic layer deposition processes. Some embodiments of the precursor delivery system comprise a reservoir with an inlet line, an outlet line and an outlet valve. Further embodiments comprise a precursor source, an inlet valve, a heater, a processing chamber and a controller. Additional embodiments relate to methods for using a precursor delivery system.

Abstract: The present disclosure relates to systems and methods for reducing the formation of hardware residue and minimizing secondary plasma formation during substrate processing in a process chamber. The process chamber may include a gas distribution member configured to flow a first gas into a process volume and generate a plasma therefrom. A second gas is supplied into a lower region of the process volume. Further, an exhaust port is disposed in the lower region to remove excess gases or by-products from the process volume during or after processing.

Abstract: Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

Abstract: Embodiments of the present disclosure generally relate to an apparatus for improving the film thickness on a substrate when using a heated substrate support. A cover plate to be placed over the top surface of a heated substrate support is disclosed. The cover plate includes a pocket formed in the middle thereof for the placement of a substrate. The cover plate may include a variety of features including a plurality of dimples, a plurality of radially disposed grooves, a plurality of annular grooves, lift pin holes, pin slots, and gas exhaust holes.

Abstract: Methods of forming a metallic-ceramic brazed joint are disclosed herein. The method of forming the brazed joint includes deoxidizing the surface of metallic components, assembling the joint, heating the joint to fuse the joint components, and cooling the joint. In certain embodiments, the brazed joint includes a conformal layer. In further embodiments, the brazed joint has features in order to reduce stress concentrations within the joint.

Abstract: A substrate support assembly includes a ground shield and a heater that is surrounded by the ground shield. The ground shield includes a plate. In one embodiment, the ground shield is composed of a ceramic body and includes an electrically conductive layer, a first protective layer on the upper surface of the plate. In another embodiment, the ground shield is composed of an electrically conductive body and a first protective layer on the upper surface of the plate.

Abstract: A method of operating a beamline ion implanter may include performing, in an ion implanter, a first implant procedure to implant a dopant of a first polarity into a given semiconductor substrate, and generating an estimated implant dose of the dopant of the first polarity based upon a set of filtered information, generated by the first implant procedure. The method may also include calculating an actual implant dose of the dopant of the first polarity using a predictive model based upon the estimated implant dose, and performing, in the ion implanter, an adjusted second implant procedure to implant a dopant of a second polarity into a select semiconductor substrate, based upon the actual implant dose.

Abstract: Analyzing a buried layer on a sample includes milling a spot on the sample using a charged particle beam of a focused ion beam (FIB) column to expose the buried layer along a sidewall of the spot. From a first perspective a first distance is measured between a first point on the sidewall corresponding to an upper surface of the buried layer and a second point on the sidewall corresponding to a lower surface of the buried layer. From a second perspective a second distance is measured between the first point on the sidewall corresponding to the upper surface of the buried layer and the second point on the sidewall corresponding to the lower surface of the buried layer. A thickness of the buried layer is determined using the first distance and the second distance.

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.