Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

Abstract: Exemplary processing methods include forming a group of LED structures on a substrate layer to form a patterned LED substrate. A light absorption barrier may be deposited on the patterned LED substrate. The methods may further include exposing the patterned LED substrate to light. The light may be absorbed by surfaces of the LED structures that are in contact with the substrate layer, and the light absorption barrier. The methods may still further include separating the LED structures for the substrate layer. The bonding between the LED structures and the substrate layer may be weakened by the absorption of the light by the surfaces of the LED structures in contact with the substrate layer.

Abstract: Exemplary methods of coating a semiconductor component substrate may include submerging the semiconductor component substrate in an alkaline electrolyte. The alkaline electrolyte may include yttrium. The methods may include igniting a plasma at a surface of the semiconductor component substrate for a period of time less than or about 12 hours. The methods may include forming a yttrium-containing oxide on the semiconductor component substrate. A surface of the yttrium-containing oxide may be characterized by a yttrium incorporation of greater than or about 10 at. %.

Abstract: Disclosed herein are methods for backside wafer dopant activation using a high-temperature ion implant. In some embodiments, a method may include forming a semiconductor device atop a first main side of a substrate, and performing a high-temperature ion implant to a second main side of the substrate, wherein the first main side of the substrate is opposite the second main side of the substrate. The method may further include performing a second ion implant to the second main side of the substrate to form a collector layer.

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

Abstract: Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component). In some embodiments, a method may include providing a plurality of device structures extending from a base, each of the plurality of device structures including a first sidewall opposite a second sidewall and a top surface extending between the first and second sidewalls, and providing a seed layer over the plurality of device structures. The method may further include forming a dielectric layer along just the top surface and along an upper portion of the first and second sidewalls using an angled deposition delivered to the plurality of device structures at a non-zero angle of inclination relative to a perpendicular extending from an upper surface of the base, and forming a fill material within one or more trenches defined by the plurality of device structures.

Abstract: A method and system for applying materials to an electronic device may include generating an electromagnetic (EM) map of the device. The EM map may indicate locations of EM radiation emitted from the electronic device. The method may also include generating a thermal map of the electronic device that may indicate locations of thermal energy emitted from the device. The method may also include generating a shielding map from the EM thermal maps. The shielding map may include instructions to control a shielding apparatus, including locations on the electronic device to apply an EM shielding material and a thermal material. The method may also include controlling a shielding apparatus to apply the EM shielding material and thermal material to the electronic device, according to the shielding map. The EM shielding material and thermal material may be applied to varying depths on the electronic device.

Abstract: Implementations disclosed herein generally relate to systems and methods of protecting a substrate support in a process chamber from cleaning fluid during a cleaning process. The method of cleaning the process chamber includes positioning in the process chamber a cover substrate above a substrate support and a process kit that separates a purge volume from a process volume. The method of cleaning includes flowing a purge gas in the purge volume to protect the substrate support and flowing a cleaning fluid to a process volume above the cover substrate, flowing the cleaning fluid in the process volume to an outer flow path, and to an exhaust outlet in the chamber body. The purge volume is maintained at a positive pressure with respect to the process volume to block the cleaning fluid from the purge volume.

Abstract: Certain embodiments provide a method and non-transitory computer readable medium having instructions that, when executed by a processor of a processing system, cause the processing system to perform a method for improving operation of a semiconductor processing system. The method of part life estimation generally includes obtaining a chamber part having a first surface portion and second surface portion. A data matrix in the first portion of the chamber part is read. The data matrix has raised features. The first portion of the chamber part is cleaned. Wear on the raised features is evaluated. The part is discarded in response to the wear on the raised feature.

Abstract: An apparatus for plasma processing of substrates is disclosed. A plasma processing chamber is provided which includes a chamber body and a lid. The lid includes a faceplate coupled to a backing plate. The faceplate and the backing plate are disposed within a processing volume defined by the chamber body and the lid. One or more ferrite blocks are coupled to the backing plate to modulate an electromagnetic field created by an RF current from an RF generator. A gas feed assembly including a gas source, a remote plasma source, and a zero field feed through are coupled to, and in fluid communication with, the processing volume through the backing plate and faceplate.

Abstract: An electrostatic chuck is described that has radio frequency coupling suitable for use in high power plasma environments. In some examples, the chuck includes a base plate, a top plate, a first electrode in the top plate proximate the top surface of the top plate to electrostatically grip a workpiece, and a second electrode in the top plate spaced apart from the first electrode, the first and second electrodes being coupled to a power supply to electrostatically charge the first electrode.

Abstract: A processing chamber may include a gas distribution member, a metal ring member below the gas distribution member, and an isolating assembly coupled with the metal ring member and isolating the metal ring member from the gas distribution member. The isolating assembly may include an outer isolating member coupled with the metal ring member. The outer isolating member may at least in part define a chamber wall. The isolating assembly may further include an inner isolating member coupled with the outer isolating member. The inner isolating member may be disposed radially inward from the metal ring member about an central axis of the processing chamber. The inner isolating member may define a plurality of openings configured to provide fluid access into a radial gap between the metal ring member and the inner isolating member.

Abstract: Apparatus and methods for processing a substrate including an injector unit, comprising a leading reactive gas port extending along a length of the injector unit, a trailing reactive gas port extending along the length of the injector unit, and a merge vacuum port forming a boundary around and enclosing the leading reactive gas port and the trailing reactive gas port.

Abstract: In large area plasma processing systems, process gases may be introduced to the chamber via the showerhead assembly which may be driven as an RF electrode. The gas feed tube, which is grounded, is electrically isolated from the showerhead. The gas feed tube may provide not only process gases, but also cleaning gases from a remote plasma source to the process chamber. The inside of the gas feed tube may remain at either a low RF field or a zero RF field to avoid premature gas breakdown within the gas feed tube that may lead to parasitic plasma formation between the gas source and the showerhead. By feeding the gas through an RF choke, the RF field and the processing gas may be introduced to the processing chamber through a common location and thus simplify the chamber design.

Abstract: Methods for depositing rhenium-containing thin films on a substrate are described. The substrate is exposed to a rhenium precursor and a reducing agent to form the rhenium-containing film (e.g., metallic rhenium, rhenium nitride, rhenium oxide, rhenium carbide). The exposures can be sequential or simultaneous. The rhenium-precursors are substantially free of halogen.

Abstract: A router may include input buffers that receive a packet being transmitted from a source to a destination, a state generator that determines a state for the packet, and a memory representing weights for actions corresponding to possible states. The memory may be configured to return an action corresponding to the state of the packet, where the action may indicate a next hop in the route between the source and the destination. The router may also include reward logic configured to generate the weights for the plurality of actions in the memory. The reward logic may receive a global reward corresponding to the route between the source and the destination, calculate a local reward corresponding to next hops available to the router; and combine the global reward and the local reward to generate the weights for the plurality of actions in the memory.

Abstract: A method of performing x-ray spectroscopy surface material analysis of a region of interest of a sample with an evaluation system that includes a scanning electron microscope (SEM) column, an x-ray detector and an x-ray polarizer, comprising: positioning a sample within a field of view of the scanning electron microscope; generating an electron beam having a landing energy about equal to an ionization energy of the materials within the region of interest of the sample; scanning the region of interest with the electron beam set to collide with the sample thereby generating x-rays emitted from near a surface of the sample, the x-rays including characteristic x-rays and Bremsstrahlung radiation; and detecting x-rays generated while the region of interest is scanned by the electron after the x-rays pass through the x-ray polarizer that blocks a higher percentage of the Bremsstrahlung radiation than the characteristic x-rays.

Abstract: Embodiments provided herein include an apparatus and methods for the plasma processing of a substrate in a processing chamber. In some embodiments, aspects of the apparatus and methods are directed to reducing defectivity in features formed on the surface of the substrate, improving plasma etch rate, and increasing selectivity of etching material to mask and/or etching material to stop layer. In some embodiments, the apparatus and methods enable processes that can be used to prevent or reduce the effect of trapped charges, disposed within features formed on a substrate, on the etch rate and defect formation.

Abstract: Exemplary processing methods of forming an LED structure may include depositing an aluminum nitride layer on a substrate via a physical vapor deposition process. The methods may include heating the aluminum nitride layer to a temperature greater than or about 1500° C. The methods may include forming an ultraviolet light emitting diode structure overlying the aluminum nitride layer utilizing a metal-organic chemical vapor deposition or molecular beam epitaxy.