Patents Assigned to Applied Material
  • SUBSTRATE HALO ARRANGEMENT FOR IMPROVED PROCESS UNIFORMITY
    Publication number: 20220384156
    Abstract: A substrate holder assembly including a substrate platen, the substrate platen disposed to support a substrate at a substrate position, a halo ring, the halo ring being disposed around the substrate position, and an outer halo being disposed around the halo ring and defining a first aperture, wherein the outer halo is disposed to engage the halo ring, the halo ring being disposed at least partially within the first aperture, the halo ring defining a second aperture, concentrically positioned within the first aperture, wherein the outer halo and the halo ring are formed at least partially of silicon, silicon carbide, doped silicon, quartz, and ceramic.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 1, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Jay R. Wallace, Simon Ruffell, Kevin R. Anglin, Tyler Rockwell, Christopher Campbell, Kevin M. Daniels, Richard J. Hertel, Kevin T. Ryan
  • DYNAMIC ACTIVATION SPARSITY IN NEURAL NETWORKS
    Publication number: 20220383121
    Abstract: A method of inducing sparsity for outputs of neural network layer may include receiving outputs from a layer of a neural network; partitioning the outputs into a plurality of partitions; identifying first partitions in the plurality of partitions that can be treated as having zero values; generating an encoding that identifies locations of the first partitions among remaining second partitions in the plurality of partitions; and sending the encoding and the second partitions to a subsequent layer in the neural network.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 1, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Tameesh Suri, Bor-Chau Juang, Nathaniel See, Bilal Shafi Sheikh, Naveed Zaman, Myron Shak, Sachin Dangayach, Udaykumar Diliprao Hanmante
  • DISPLACEMENT MEASUREMENTS IN SEMICONDUCTOR WAFER PROCESSING
    Publication number: 20220384221
    Abstract: Wafers that begin as flat surfaces during a semiconductor manufacturing process may become warped or bowed as layers and features are added to an underlying substrate. This warpage may be detected between manufacturing processes by rotating the wafer adjacent to a displacement sensor. The displacement sensor may generate displacement data relative to a baseline measurement to identify areas of the wafer that bow up or down. The displacement data may then be mapped to locations on the wafer relative to an alignment feature. This mapping may then be used to adjust parameters in subsequent semiconductor processes, including adjusting how a carrier head on a polishing process holds or applies pressure to the wafer as it is polished. A model may be trained to provide control signals for a polishing/cleaning process, or to generate metrology data.
    Type: Application
    Filed: April 27, 2022
    Publication date: December 1, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Justin H. Wong, Ehud Chatow
  • V-NAND STACKS WITH DIPOLE REGIONS
    Publication number: 20220384469
    Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 1, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Yong Yang, Jacqueline S. Wrench, Yixiong Yang, Pradeep K. Subrahmanyan, Srinivas Gandikota
  • DISPLACEMENT MEASUREMENTS IN SEMICONDUCTOR WAFER PROCESSING
    Publication number: 20220384278
    Abstract: Wafers that begin as flat surfaces during a semiconductor manufacturing process may become warped or bowed as layers and features are added to an underlying substrate. This warpage may be detected between manufacturing processes by rotating the wafer adjacent to a displacement sensor. The displacement sensor may generate displacement data relative to a baseline measurement to identify areas of the wafer that bow up or down. The displacement data may then be mapped to locations on the wafer relative to an alignment feature. This mapping may then be used to adjust parameters in subsequent semiconductor processes, including adjusting how a carrier head on a polishing process holds or applies pressure to the wafer as it is polished.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Justin Wong, Ehud Chatow
  • Methods of Lowering Deposition Rate
    Publication number: 20220380897
    Abstract: A deposition method demonstrating a slower growth rate is disclosed. Some embodiments of the disclosure provide CVD methods which utilize a halide-containing growth inhibitor as a co-reactant with a metal halide precursor and a reactant. Some embodiments of the disclosure relate to CVD and ALD methods comprising exposure of the substrate surface to a pretreatment comprising a halide-containing growth inhibitor.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 1, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Kunal Bhatnagar, Mohith Verghese
  • METAL-DOPED CARBON HARDMASKS
    Publication number: 20220384188
    Abstract: Exemplary deposition methods may include delivering a ruthenium-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. At least one of the ruthenium-containing precursor or the hydrogen-containing precursor may include carbon. The methods may include forming a plasma of all precursors within the processing region of a semiconductor processing chamber. The methods may include depositing a ruthenium-and-carbon material on a substrate disposed within the processing region of the semiconductor processing chamber.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 1, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Eswaranand Venkatasubramanian, Bhaskar Jyoti Bhuyan, Mark J. Saly, Abhijit Basu Mallick
  • Fast response pedestal assembly for selective preclean
    Patent number: 11515130
    Abstract: Implementations of the present disclosure generally relate to an improved substrate support pedestal assembly. In one implementation, the substrate support pedestal assembly includes a shaft. The substrate support pedestal assembly further includes a substrate support pedestal, mechanically coupled to the shaft. The substrate support pedestal comprises substrate support plate coated on a top surface with a ceramic material.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Lara Hawrylchak, Chaitanya A. Prasad
  • Low temperature graphene growth
    Patent number: 11515163
    Abstract: Exemplary methods of semiconductor processing may include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The methods may include generating a plasma of the carbon-containing precursor and the hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C. The methods may include halting flow of the carbon-containing precursor while maintaining the plasma with the hydrogen-containing precursor.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Jialiang Wang, Susmit Singha Roy, Abhijit Basu Mallick, Nitin K. Ingle
  • Selective deposition of a passivation film
    Patent number: 11515154
    Abstract: Selective deposition methods are described. An exemplary method comprises exposing the substrate comprising a first surface and a second surface to an anchor reactant and selectively depositing the anchor reactant on the first surface as a seed layer, wherein the anchor reactant comprises an ethynyl derivative with a headgroup that selectively targets the first surface.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Andrea Leoncini, Yong Wang, Doreen Wei Ying Yong
  • Polishing system with support post and annular platen or polishing pad
    Patent number: 11511388
    Abstract: A polishing system includes a platen having a top surface to support an annular polishing pad, a carrier head to hold a substrate in contact with the annular polishing pad, a support structure extending above the platen and to which one or more polishing system components are secured, and a support post. The platen is rotatable about an axis of rotation that passes through approximately a center of the platen. The first support post has an upper end coupled to and supporting the support structure and a lower portion that is supported on the platen or that extends through an aperture in the platen.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Paul D. Butterfield, Thomas H. Osterheld, Jeonghoon Oh, Shou-Sung Chang, Steven M. Zuniga, Fred C. Redeker
  • Semiconductor processing chamber multistage mixing apparatus
    Patent number: 11515179
    Abstract: Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Mehmet Tugrul Samir, Dongqing Yang
  • Graded dimple height pattern on heater for lower backside damage and low chucking voltage
    Patent number: 11515191
    Abstract: Embodiments disclosed herein may include a heater pedestal. In an embodiment, the heater pedestal may comprise a heater pedestal body and a conductive mesh embedded in the heater pedestal. In an embodiment, the conductive mesh is electrically coupled to a voltage source In an embodiment, the heater pedestal may further comprise a support surface on the heater pedestal body. In an embodiment, the support surface comprises a plurality of pillars extending out from the heater pedestal body and arranged in concentric rings. In an embodiment pillars in an outermost concentric ring have a height that is greater than a height of pillars in an innermost concentric ring.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Vivek B. Shah, Bhaskar Kumar, Ganesh Balasubramanian
  • Hardmask tuning by electrode adjustment
    Patent number: 11515150
    Abstract: Exemplary processing methods may include forming a plasma of a deposition precursor in a processing region of a semiconductor processing chamber. The methods may include adjusting a variable capacitor within 20% of a resonance peak. The variable capacitor may be coupled with an electrode incorporated within a substrate support on which a substrate is seated. The methods may include depositing a material on the substrate.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Michael Wenyoung Tsiang, Abdul Aziz Khaja, Li-Qun Xia, Kevin Hsiao, Liangfa Hu, Yayun Cheng
  • Substrate flipping device
    Patent number: 11511950
    Abstract: A substrate flipping device includes a substrate securing assembly, a gripping actuator, and a rotary actuator. The gripping actuator is configured to pneumatically cause the substrate securing assembly to be in an open position to receive a substrate and configured to pneumatically cause the substrate securing assembly to be in a closed position to secure the substrate. The rotary actuator is configured to pneumatically cause the substrate securing assembly to rotate to a flipped position and to pneumatically rotate to a non-flipped position.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Michael Minh Phan, Steven Trey Tindel, Paul Benjamin Reuter
  • Physical vapor deposition processing systems target cooling
    Patent number: 11515132
    Abstract: Physical vapor deposition target assemblies and methods of manufacturing such target assemblies are disclosed. An exemplary target assembly comprises a flow pattern including a plurality of arcs and bends fluidly connected to an inlet end and an outlet end.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Sanjay Bhat, Vibhu Jindal, Vishwas Kumar Pandey
  • Process kit for a high throughput processing chamber
    Patent number: 11512391
    Abstract: A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Kalyanjit Ghosh, Mayur G. Kulkarni, Sanjeev Baluja, Kien N. Chuc, Sungjin Kim, Yanjie Wang
  • Pivotable substrate retaining ring
    Patent number: 11511390
    Abstract: A carrier head includes a base assembly, a substrate mounting surface connected to the base assembly, and a plurality of segments disposed circumferentially around the substrate mounting surface to provide a retaining ring to surround a substrate mounted on the substrate mounting surface. An inner surface of each of the plurality of segments is configured to engage the substrate, and each segment of the plurality of segments of the retaining ring is pivotally connected to the base assembly such that a lower portion of each segment of the retaining ring is swingable toward and away from the substrate.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Steven M. Zuniga, Jay Gurusamy, Andrew J. Nagengast
  • Characterizing and monitoring electrical components of manufacturing equipment
    Patent number: 11513504
    Abstract: A method includes receiving, from one or more sensors associated with manufacturing equipment, current trace data associated with producing, by the manufacturing equipment, a plurality of products. The method further includes performing signal processing to break down the current trace data into a plurality of sets of current component data mapped to corresponding component identifiers. The method further includes providing the plurality of sets of current component data and the corresponding component identifiers as input to a trained machine learning model. The method further includes obtaining, from the trained machine learning model, one or more outputs indicative of predictive data and causing, based on the predictive data, performance of one or more corrective actions associated with the manufacturing equipment.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventor: David John Paul
  • Thermally controlled lid stack components
    Patent number: 11515176
    Abstract: Exemplary substrate processing systems may include chamber body defining a transfer region. The systems may include a lid plate seated on the chamber body. The lid plate may define a first plurality of apertures through the lid plate and a second plurality of apertures through the lid plate. The systems may include a plurality of lid stacks equal to a number of apertures of the first plurality of apertures defined through the lid plate. Each lid stack of the plurality of lid stacks may include a choke plate seated on the lid plate along a first surface of the choke plate. The choke plate may define a first aperture axially aligned with an associated aperture of the first plurality of apertures. The choke plate may define a second aperture axially aligned with an associated aperture of the second plurality of apertures.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Siva Chandrasekar, Satish Radhakrishnan, Rajath Kumar Lakkenahalli Hiriyannaiah, Viren Kalsekar, Vinay Prabhakar