Abstract: In one example, a chamber inlet assembly includes a chamber inlet, an outer coupling for a delivery line, and an inner coupling for a processing region of a processing chamber. The inner coupling and the outer coupling are on inner and outer ends, respectively, of the chamber inlet, wherein a cross-sectional area of the inner coupling is larger than a cross-sectional area of the outer coupling. The chamber inlet assembly also includes a longitudinal profile including the inner and outer ends and a first side and a second side, the first and second sides being on opposite sides of the chamber inlet, wherein a shape of the longitudinal profile comprises at least one of triangular, modified triangular, trapezoidal, modified trapezoidal, rectangular, modified rectangular, rhomboidal, and modified rhomboidal. The chamber inlet assembly also includes cassette including the chamber inlet and configured to set into a side wall of the processing chamber.

Abstract: Embodiments disclosed herein include an optical sensor system for use in plasma processing tools. In an embodiment, the optical sensor system, comprises an optically clear body with a first surface and a second surface facing away from the first surface. In an embodiment, the optically clear body further comprises a third surface that is recessed from the second surface. In an embodiment, the optical sensor system further comprises a target over the third surface and a first reflector to optically couple the first surface to the target.

Abstract: A substrate etching system includes a support to hold a wafer in a face-up orientation, a dispenser arm movable laterally across the wafer on the support, the dispenser arm supporting a delivery port to selectively dispense a liquid etchant onto a portion of a top face of the wafer, and a monitoring system comprising a probe movable laterally across the wafer on the support.

Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The assemblies may include a support stem coupled with the electrostatic chuck body. The assemblies may include a heater embedded within the electrostatic chuck body. The assemblies may also include an electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The substrate support assemblies may be characterized by a leakage current through the electrostatic chuck body of less than or about 4 mA at a temperature of greater than or about 500° C. and a voltage of greater than or about 600 V.

Abstract: An apparatus and method of processing a workpiece is disclosed, where a sacrificial capping layer is created on a top surface of a workpiece. That workpiece is then exposed to an ion implantation process, where select species are used to passivate the workpiece. While the implant process is ongoing, radicals and excited species etch the sacrificial capping layer. This reduces the amount of etching that the workpiece experiences. In certain embodiments, the thickness of the sacrificial capping layer is selected based on the total time used for the implant process and the etch rate. The total time used for the implant process may be a function of desired dose, bias voltage, plasma power and other parameters. In some embodiments, the sacrificial capping layer is applied prior to the implant process. In other embodiments, material is added to the sacrificial capping layer during the implant process.

Abstract: Exemplary semiconductor processing chambers may include a substrate support positioned within a processing region of the semiconductor processing chamber. The chamber may include a lid plate. The chamber may include a gasbox positioned between the lid plate and the substrate support. The gasbox may be characterized by a first surface and a second surface opposite the first surface. The gasbox may define a central aperture. The gasbox may define an annular channel in the first surface of the gasbox extending about the central aperture through the gasbox. The gasbox may include an annular cover extending across the annular channel defined in the first surface of the gasbox. The chamber may include a blocker plate positioned between the gasbox and the substrate support. The chamber may include a ferrite block positioned between the lid plate and the blocker plate.

Abstract: Embodiments of the present disclosure generally relate to substrate support assemblies used in semiconductor device manufacturing. In one embodiment, a substrate support includes a ceramic body having at least one aperture formed therein defined by a sidewall. A plurality of recesses extend into the sidewall, a rod member is disposed in the at least one aperture, and an eyelet member is circumferentially disposed about the rod member. The eyelet member has a plurality of protrusions extending outwardly therefrom, each disposed in a corresponding recess of the plurality of recesses. A first portion of each protrusion is in contact with a sidewall of the respective recess of the ceramic body and a second portion of each protrusion is separated by a gap from the sidewall of the respective recess of the ceramic body. A first portion of a brazing material is disposed between an upper surface of the at least one aperture and an end of the rod member.

Abstract: A system includes a robot arm with multiple joints and one or more end effector to carry a substrate. A processing device determines, within joint space of the robot arm, start/end points of the one or more end effector for a complete movement. The processing device builds, in joint space for the multiple joints and the one or more end effector, a graph of reachable positions and sub-paths between the reachable positions that satisfy Cartesian limits. The reachable positions are identified at a granularity that divides the complete movement into multiple sub-movements. The processing device executes a graph optimization algorithm on the graph to determine multiple paths, each a group of the sub-paths, that have one of shortest distances or lowest costs between the start/end points, and selects a path thereof that minimizes move time of the one or more end effector between the start/end points.

Abstract: Embodiments described herein relate to a precision dynamic leveling mechanism for repeatedly positioning the pedestal within a process. The precision dynamic leveling mechanism includes bearing assemblies. Bearing assemblies having inner races forced against a pedestal assembly carrier and outer races forced against a guide adaptor provide nominal clearance between the inner races and outer races to allow the inner races and the outer races to slide on each other with minimal or no radial motion.

Abstract: Exemplary methods of etching may include flowing a fluorine-containing precursor and a secondary gas into a processing region of a semiconductor processing chamber. The secondary gas may be or include oxygen or nitrogen. A flow rate ratio of the fluorine-containing precursor to the secondary gas may be greater than or about 1:1. The methods may include contacting a substrate with the fluorine-containing precursor and the secondary gas. The substrate may include an exposed metal. The substrate may define a high aspect-ratio structure. The methods may include etching the exposed metal within the high aspect-ratio structure.

Abstract: Power supplies, waveform function generators and methods for controlling a plasma process are described. The power supplies or waveform function generators include a component for executing the method in which a waveform shape change index is determined during a plasma process and evaluated for compliance with a predetermined tolerance.

Abstract: A network-on-package (NoPK) for connecting a plurality of chiplets may include a plurality of interface bridges configured to convert a plurality of protocols used by the plurality of chiplets into a common protocol, a routing network configured to route traffic between the plurality of interface bridges using the common protocol, and a controller configured to program the plurality of interface bridges and the routing network based on types of the plurality of chiplets connected to the NoPK. The NoPK may provide a scalable connection for any number of chiplets from different ecosystems using different communication protocols.

Abstract: Pump liners and process chambers with the pump liners are described. The pump liner has a ring-shaped body with an annular wall enclosing a process region. A plurality of circumferentially spaced openings provide fluid communication through the annular wall between the process region and a region outside of the ring-shaped body. Each of the plurality of circumferentially spaced openings has a self-adjusting valve assembly. Self-adjusting valves and processing methods are also described.

Abstract: Methods for patterning a substrate are described. A substrate is scanned using a spatial light modulator with a plurality of exposures timed according to a non-crystalline shot pattern. Lithography systems for performing the substrate patterning method and non-transitory computer-readable medium for executing the patterning method are also described.

Abstract: Methods, systems and apparatus for decreasing total distortion of a maskless lithography process are disclosed. Some embodiments provide methods, systems and apparatus for decreasing total distortion without physical modification of the apparatus.

Abstract: Molybdenum(0) and coordination complexes are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum disulfide, molybdenum nitride). The exposures can be sequential or simultaneous.

Abstract: Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

Abstract: Methods of forming memory devices are described. A molybdenum silicide nucleation layer is formed, and the substrate is soaked in a titanium precursor prior to a bulk molybdenum gap fill process. In other embodiments, a molybdenum silicide film is formed in a first process cycle and a second process cycle is performed where the substrate is exposed to a titanium precursor. In further embodiments, a substrate having at least one feature thereon is exposed to a first titanium precursor and a nitrogen-containing reactant. The substrate is then soaked in a second titanium precursor, and then is exposed to a first molybdenum precursor followed by exposure to a silane to form a molybdenum silicide layer on a surface of the substrate.

Abstract: A method of forming a metal oxide semiconductor field effect transistor with improved gate-induced drain leakage performance, the method including providing a semiconductor substrate having a gate trench formed therein, performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.