Abstract: Methods and systems for forming films on substrates in semiconductor processes are disclosed. The method includes providing different materials each contained in separate ampoules. Material is flowed from each ampoule into a separate portion of a showerhead contained within a process chamber via a heated gas line. From the showerhead, each material is flowed on to a substrate that sits on the surface of a rotating pedestal. Controlling the mass flow rate out of the showerhead and the rotation rate of the pedestal helps result in films with desirable material domain sizes to be deposited on the substrate.

Abstract: Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

Abstract: An apparatus for chemical mechanical polishing includes a platen having a surface to support a polishing pad, a carrier head to hold a substrate against a polishing surface of the polishing pad, a pad conditioner to hold a conditioning disk against the polishing surface, an in-situ polishing pad thickness monitoring system; and, a controller configured to receive a signal from the monitoring system and generate a measure of polishing pad wear rate by applying a predictive filter to the signal.

Abstract: Embodiments described herein generally related to a substrate processing apparatus, and more specifically to an improved showerhead assembly for a substrate processing apparatus. The showerhead assembly includes a chill plate, a gas plate, and a gas distribution plate having a top surface and a bottom surface. A plurality of protruded features contacts the top surface of the gas distribution plate. A fastener and an energy storage structure is provided on the protruded features. The energy storage structure is compressed by the fastener and axially loads at least one of the protruded features to compress the chill plate, the gas plate and the gas distribution plate.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: Electronic device processing systems including an equipment front end module with at least one side storage pod are described. The side storage pod has a chamber including a top substrate holder and a bottom substrate holder. In some embodiments, an exhaust port is located at a midpoint between the top substrate holder and the bottom substrate holder. Methods and systems in accordance with these and other embodiments are also disclosed.

Abstract: A method of generating training spectra for training of a neural network includes generating a plurality of theoretically generated initial spectra from an optical model, sending the plurality of theoretically generated initial spectra to a feedforward neural network to generate a plurality of modified theoretically generated spectra, sending an output of the feedforward neural network and empirically collected spectra to a discriminatory convolutional neural network, determining that the discriminatory convolutional neural network does not discriminate between the modified theoretically generated spectra and empirically collected spectra, and thereafter, generating a plurality of training spectra from the feedforward neural network.

Abstract: A semiconductor processing chamber for processing semiconductor substrates may include a pedestal to support a substrate with a heater zones and a wire mesh configured to deliver a Radio Frequency (RF) signal to a plasma. The chamber may also include heater zone controls that deliver current to the heater zones and a filter circuit between the heater zone controls and the heater zones. The filter circuit may include inductors on leads from the heater zones and a resonant circuit with a resonant inductor that is magnetically coupled to the lead inductors. The resonant circuit may produce a resonant peak that filters the RF signal delivered to the wire mesh from the leads from the heater zones to prevent the RF signal from reaching the heater zone controls.

Abstract: Embodiments of the disclosure relate to methods of depositing tungsten. Some embodiments of the disclosure provide methods for depositing tungsten which are performed at relatively low temperatures. Some embodiments of the disclosure provide methods in which the ratio between reactant gasses is controlled. Some embodiments of the disclosure provide selective deposition of tungsten. Some embodiments of the disclosure provide methods for depositing tungsten films at a low temperature with relatively low roughness, stress and impurity levels.

Abstract: Methods of semiconductor processing may include performing a first plasma treatment within a processing chamber to remove a first carbon-containing material. The methods may include performing a second plasma treatment within the processing chamber to remove a first silicon-containing material. The methods may include depositing a second silicon-containing material on surfaces of the processing chamber. The methods may include depositing a second carbon-containing material overlying the second silicon-containing material.

Abstract: A method may include providing a substrate having, on a first surface of the substrate, a low dielectric constant layer characterized by a layer thickness. The method may include heating the substrate to a substrate temperature in a range of 200° C. to 550° C.; and directing an ion implant treatment to the low dielectric constant layer, while the substrate temperature is in the range of 200° C. to 550° C. As such, the ion implant treatment may include implanting a low weight ion species, at an ion energy generating an implant depth equal to 40% to 175% of the layer thickness.

Abstract: Methods and film stacks for extreme ultraviolet (EUV) lithography are described. The film stack comprises a substrate with a hard mask, bottom layer, middle layer and photoresist. Etching of the photoresist is highly selective to the middle layer and a modification of the middle layer allows for a highly selective etch relative to the bottom layer.

Abstract: Some embodiments of the disclosure relate to methods of modifying a heater pedestal to improve temperature and thickness uniformity. Some embodiments of the disclosure relate to the modified heater pedestals with improved temperature and thickness uniformity. In some embodiments, the height of support mesas in different regions of the pedestal are modified to increase temperature uniformity. In some embodiments, the heater elements are moved above the vacuum channel and purge channel to increase temperature uniformity. In some embodiments, the edge ring is modified to be coplanar with the top of a supported substrate.

Abstract: Packaging materials and methods of manufacture are disclosed. The packaging material comprises a substrate surface and film coating selected from the group consisting of an elastomer, a polymer, an inorganic material and combinations thereof. The film coating includes a first layer and a second layer, the first layer deposited on the second layer. The first layer has a formula of SiOxNyCz, where x is in a range from 1.9 to 2.15, y is in a range from 0.01 to 0.08, and z is in a range from 0.10 to 0.40.

Abstract: Memory devices and methods of manufacturing memory devices are provided. The device and methods described decrease the resistivity of word lines by forming word lines comprising low resistivity materials. The low resistivity material has a resistivity in a range of from 5 ??cm to 100 ??cm. Low resistivity materials may be formed by recessing the word line and selectively growing the low resistivity materials in the recessed portion of the word line. Alternatively, low resistivity materials may be formed by depositing a metal layer and silicidating the metal in the word line region and in the common source line region.

Abstract: Pumping liners for process chambers including a first ring-shaped body and a second ring-shaped body are described. The first ring-shaped body has a first plurality of openings and the second ring-shaped body has a second plurality of openings. The first ring-shaped body and the second ring-shaped body are rotatable relative to each other around a central axis to at least partially overlap the first plurality of openings and the second plurality of openings to change the area of conductance through the openings. Methods of removing gases from a processing chamber are also described.

Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.

Abstract: A method of performing x-ray spectroscopy material analysis of a region of interest within a cross-section of a sample using an evaluation system that includes a focused ion beam (FIB) column, a scanning electron microscope (SEM) column, and an x-ray detector, including: forming a lamella having first and second opposing side surfaces in the sample by milling, with the FIB column, first and second trenches in the sample to expose the first and second sides surface of the lamella, respectively; depositing background material in the second trench, wherein the background material is selected such that the background material does not include any chemical elements that are expected to be within the region of interest of the sample; generating a charged particle beam with the SEM column and scanning the charged particle beam across a region of interest on the first side surface of the lamella such that the charged particle beam collides with the first side surface of the lamella at a non-vertical angle; and detect

Abstract: To protect against physical and side-channel attacks, circuit assemblies may mount a main processor opposite of a cryptographic processor such that traces between the two processors are hidden in a substrate. Another substrate defining a cavity may be mounted on the bottom of the substrate to enclose the cryptographic processor and prevent physical access without disrupting the cryptographic operations. Voltage converters with integrated inductors may also be included in the cavity to generate electromagnetic noise that will disrupt the sensitive equipment used in side-channel attacks. An electromagnetic shield may be sputtered on top of the main processor to block electromagnetic sniffing attacks while still allowing the processor to be coupled with a heat sink.

Abstract: Embodiments described herein include an applicator frame for a processing chamber. In an embodiment, the applicator frame comprises a first major surface of the applicator frame and a second major surface of the applicator frame opposite the first major surface. In an embodiment, the applicator frame further comprises a through hole, wherein the through hole extends entirely through the applicator frame. In an embodiment, the applicator frame also comprises a lateral channel embedded in the applicator frame. In an embodiment the lateral channel intersects the through hole.