Abstract: Methods for forming a semiconductor structure are described. The method includes cleaning a substrate to form a substrate surface substantially free of oxide, exposing the substrate surface to a first molybdenum precursor, and exposing the substrate surface to a reactant to selectively deposit a first molybdenum film on the substrate surface. The method may be performed in a processing chamber without breaking vacuum. The method may also include forming one or more of a cap layer and a liner and annealing the substrate. The method may also include depositing a second molybdenum film on the substrate surface.

Abstract: An extreme ultraviolet mask and method of manufacture thereof includes: providing a glass-ceramic block; forming a glass-ceramic substrate from the glass-ceramic block; and depositing a planarization layer on the glass-ceramic substrate.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.

Abstract: Embodiments of this disclosure include a method of processing a substrate that includes etching a first dielectric material formed on a substrate that is disposed on a substrate supporting surface of a substrate support assembly disposed within a processing region of a plasma processing chamber. The etching process may include delivering a process gas to the processing region, wherein the process gas comprises a first fluorocarbon containing gas and a first process gas, delivering, by use of a radio frequency generator, a radio frequency signal to a first electrode to form a plasma in the processing region, and establishing, by use of a first pulsed-voltage waveform generator, a first pulsed voltage waveform at a biasing electrode disposed within the substrate support assembly.

Abstract: Exemplary substrate support assemblies include an electrostatic chuck body defining a substrate platform. The substrate platform may be characterized by an upper surface. The platform may define a purge aperture. The platform may include a plurality of mesas that are disposed in an inner region of the upper surface. Each of the mesas may protrude upward from the upper surface. The platform may include a sealing band that extends upward from the upper surface in a circumferential pattern and partially encircles the inner region of the upper surface. Top surfaces of the mesas and sealing band may form a support surface for a substrate. The sealing band may define a number of gaps. The assemblies may include a support stem coupled with the electrostatic chuck body, a heater embedded within the electrostatic chuck body, and a backside gas source that is coupled with the purge aperture of the support surface.

Abstract: A pedestal for a thermal treatment chamber is disclosed that includes a body consisting of an optically transparent material. The body includes a first plate with a perforated surface having a plurality of nozzles formed therein, a first portion of the plurality nozzles formed in the body at an angle that is orthogonal to a plane of the first plate, a second portion of the plurality of nozzles formed in the body in an azimuthal orientation and at an acute angle relative to the plane of the first plate, and a third portion of the plurality nozzles formed in the body in a radial orientation and at an acute angle relative to the plane of the first plate.

Abstract: Embodiments described herein generally relate to apparatus for fabricating semiconductor devices. A gas injection apparatus is coupled to a first gas source and a second gas source. Gases from the first gas source and second gas source may remain separated until the gases enter a process volume in a process chamber. A coolant is flowed through a channel in the gas injection apparatus to cool the first gas and the second gas in the gas injection apparatus. The coolant functions to prevent thermal decomposition of the gases by mitigating the influence of thermal radiation from the process chamber. In one embodiment, the channel surrounds a first conduit with the first gas and a second conduit with the second gas.

Abstract: An ion beam processing system including a plasma chamber, a plasma plate, disposed alongside the plasma chamber, the plasma plate defining a first extraction aperture, a beam blocker, disposed within the plasma chamber and facing the extraction aperture, a blocker electrode, disposed on a surface of the beam blocker outside of the plasma chamber, and an extraction electrode disposed on a surface of the plasma plate outside of the plasma chamber.

Abstract: Examples of the present technology include semiconductor processing methods to form boron-containing materials on substrates. Exemplary processing methods may include delivering a deposition precursor that includes a boron-containing precursor to a processing region of a semiconductor processing chamber. A plasma may be formed from the deposition precursor within the processing region of the semiconductor processing chamber. The methods may further include depositing a boron-containing material on a substrate disposed within the processing region of the semiconductor processing chamber, where the substrate is characterized by a temperature of less than or about 50° C. The as-deposited boron-containing material may be characterized by a surface roughness of less than or about 2 nm, and a stress level of less-than or about ?500 MPa. In some embodiments, a layer of the boron-containing material may function as a hardmask.

Abstract: Aspects of the present disclosure relate generally to isolator devices, components thereof, and methods associated therewith for substrate processing chambers. In one implementation, a substrate processing chamber includes an isolator ring disposed between a pedestal and a pumping liner. The isolator ring includes a first surface that faces the pedestal, the first surface being disposed at a gap from an outer circumferential surface of the pedestal. The isolator ring also includes a second surface that faces the pumping liner and a protrusion that protrudes from the first surface of the isolator ring and towards the outer circumferential surface of the pedestal. The protrusion defines a necked portion of the gap between the pedestal and the isolator ring.

Abstract: Disclosed are approaches for 3D NAND structure fabrication. One method may include providing a stack of layers comprising a first and second plurality of layers, and forming a plurality of trenches in the stack of layers, wherein each of the trenches includes a tiered sidewall. A first trench may be formed to a first depth, and a second trench may be formed to a second depth, which is greater than the first depth. The method may further include forming a liner within the trenches, wherein the liner is deposited at a non-zero angle of inclination relative to a normal extending perpendicular from the top surface of the stack of layers. The liner may have a first thickness along the tiered sidewall of the first trench and a second thickness along the tiered sidewall of the second trench, wherein the first thickness is greater than the second thickness.

Abstract: Methods and precursors for depositing metal fluoride films on a substrate surface are described. The method includes exposing the substrate surface to a metal precursor and a fluoride precursor. The fluoride precursor is volatile at a temperature in a range of from 20° C. to 200° C. The metal precursor reacts with the fluoride precursor to form a non-volatile metal fluoride film.

Abstract: Exemplary etching methods may include flowing a fluorine-containing precursor and a hydrogen-containing precursor into a remote plasma region of a semiconductor processing chamber. The methods may include forming a plasma of the fluorine-containing precursor and the hydrogen-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents into a substrate processing region housing a substrate. The substrate may include an exposed region of a tantalum or titanium material and an exposed region of a silicon-containing material. The methods may include contacting the substrate with the plasma effluents. The methods may include removing the tantalum or titanium material selectively to the silicon-containing material. The tantalum or titanium material may be removed at a rate of at least 20:1 relative to the silicon-containing material.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise an absorber layer comprising a material selected from the group consisting of ruthenium (Ru) and one or more elements of Group 1, Ru and one or more elements of Group 1 and one or more elements of Group 2, Ru and one or more elements of Group 1 and tantalum (Ta), Ru and one or more elements of Group 1 and Ta and one or more elements of Group 2, tellurium (Te) and nickel (Ni), and tellurium (Te) and aluminum (Al).

Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where a spacer is formed around each of the bit line contact pillars, the spacer in contact with the spacer of an adjacent bit line contact pillar. A doped layer is then epitaxially grown on the memory stack and bit line is formed on the memory stack. The bit line is self-aligned with the active region.

Abstract: Exemplary etching methods may include forming a plasma of a fluorine-containing precursor to produce plasma effluents. A first bias frequency may be applied while forming the plasma. The methods may include contacting a substrate housed in a processing region of a semiconductor processing chamber with the plasma effluents. The substrate may be or include a photomask. The methods may include etching a first layer of the photomask. Etching the first layer of the photomask may expose a second layer of the photomask. The methods may include adjusting the first bias frequency to a second bias frequency while maintaining the plasma of the fluorine-containing precursor. The methods may include etching the second layer of the photomask.

Abstract: A method of evaluating a region of a sample, the method comprising: positioning a sample within a vacuum chamber; generating an electron beam with a scanning electron microscope (SEM) column that includes an electron gun at one end of the column and a column cap at an opposite end of the column; focusing the electron beam on the sample and scanning the focused electron beam across the region of the sample, while the SEM column is operated in tilted mode, thereby generating secondary electrons and backscattered electrons from within the region; and during the scanning, collecting backscattered electrons with one or more detectors while applying a negative bias voltage to the column cap to alter a trajectory of the secondary electrons preventing the secondary electrons from reaching the one or more detectors.

Abstract: Exemplary lithography mask processing chambers may include a substrate support that includes a plurality of lift pins that are vertically translatable relative to a top surface of the substrate support. The lithography mask processing chambers may include a cover ring positioned atop the substrate support. The cover ring may define a rectilinear substrate seat. A top surface of the rectilinear substrate seat may be elevated above the top surface of the substrate support. An outer periphery of the rectilinear substrate seat may be positioned outward of the plurality of lift pins.

Abstract: A method of fabricating a piezoelectric layer includes depositing a piezoelectric material onto a substrate in a first crystallographic phase by physical vapor deposition while the substrate remains at a temperature below 400° C., and thermally annealing the substrate at a temperature above 500° C. to convert the piezoelectric material to a second crystallographic phase. The physical vapor deposition includes sputtering from a target in a plasma deposition chamber.

Abstract: The present disclosure relates to methods and systems for chucking in substrate processing chambers. In one implementation, a method of chucking one or more substrates in a substrate processing chamber includes applying a chucking voltage to a pedestal. A substrate is disposed on a support surface of the pedestal. The method also includes ramping the chucking voltage from the applied voltage, detecting an impedance shift while ramping the chucking voltage, determining a corresponding chucking voltage at which the impedance shift occurs, and determining a refined chucking voltage based on the impedance shift and the corresponding chucking voltage.