Abstract: Chemical-mechanical polishing assemblies may include an upper platen characterized by a first surface and a second surface opposite the first surface. The upper platen may define a recess in the second surface of the upper platen. The upper platen may define a flexure between the first surface and the second surface within the recess. The assemblies may include a polishing pad coupled with the first surface of the upper platen. The assemblies may include a plate coupled with the upper platen along the second surface of the upper platen. The plate may define a volume within the recess of the upper platen between the second surface of the upper platen and the plate.

Abstract: Exemplary semiconductor processing chambers may include a substrate support including a top surface. A peripheral edge region of the top surface may be recessed relative to a medial region of the top surface. The chambers may include a pumping liner disposed about an exterior surface of the substrate support. The chambers may include a liner disposed between the substrate support and the pumping liner. The liner may be spaced apart from the exterior surface to define a purge lumen between the liner and the substrate support. The chambers may include an edge ring seated on the peripheral edge region. The edge ring may extend beyond a peripheral edge of the substrate support and above a portion of the liner. A gap may be formed between a bottom surface of the edge ring and a top surface of the liner. The gap and the purge lumen may be fluidly coupled.

Abstract: Molybdenum(IV) and molybdenum(III) coordination complexes are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum nitride). The exposures can be sequential or simultaneous.

Abstract: A heater assembly having a backside purge gap formed between a top plate and a heater of the heater assembly, the top plate having a top plate wall. The top plate wall having an upper portion, a middle portion and a lower portion, the middle portion forming an incline relative to the top portion.

Abstract: Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a first lid plate seated on the chamber body. The first lid plate may define a plurality of apertures through the first lid plate. The systems may include a plurality of lid stacks equal to a number of the plurality of apertures. The systems may define a plurality of isolators. An isolator may be positioned between each lid stack and a corresponding aperture of the plurality of apertures. The systems may include a plurality of annular spacers. An annular spacer of the plurality of annular spacers may be positioned between each isolator and a corresponding lid stack of the plurality of lids stacks. The systems may include a plurality of manifolds. A manifold may be seated within an interior of each annular spacer of the plurality of annular spacers.

Abstract: Exemplary semiconductor processing systems may include an output manifold that defines at least one plasma outlet. The systems may include a gasbox disposed beneath the output manifold. The gasbox may include an inlet side facing the output manifold and an outlet side opposite the inlet side. The gasbox may include an inner wall that defines a central fluid lumen. The inner wall may taper outward from the inlet side to the outlet side. The systems may include an annular spacer disposed below the gasbox. An inner diameter of the annular spacer may be greater than a largest inner diameter of the central fluid lumen. The systems may include a faceplate disposed beneath the annular spacer. The faceplate may define a plurality of apertures extending through a thickness of the faceplate.

Abstract: Process chamber, high voltage measurement systems and methods for monitoring the output of a high voltage power supply are described. The output of the high voltage power supply is converted using a transducer and measured with high accuracy. A high voltage measurement system compares the converted value with a threshold criterion and actuates an interlock if readings are outside the threshold.

Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.

Abstract: Methods of forming a stack without damaging underlying layers are discussed. The encapsulation layer and dielectric layer are highly conformal, have low etch rates, and good hermeticity. These films may be used to protect chalcogen materials in PCRAM devices or any substrates sensitive to oxygen or moisture. Some embodiments utilize a two-step process comprising a first ALD process to form an encapsulation layer and oxidation process to form a dielectric layer.

Abstract: Methods for plasma enhanced atomic layer deposition (PEALD) of low-? films are described. A method of depositing a film comprises exposing a substrate to a silicon precursor having the general formula (I) wherein R1, R2, R3, R4, R5, and R6 are independently selected from hydrogen (H), substituted alkyl, or unsubstituted alkyl; purging the processing chamber of the silicon precursor; exposing the substrate to a carbon monoxide (CO) plasma to form one or more of a silicon oxycarbide (SiOC) or silicon oxycarbonitride (SiOCN) film on the substrate; and purging the processing chamber.

Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

Abstract: Methods of coating extreme ultraviolet (EUV) reticle carrier assemblies are disclosed. The method includes depositing an adhesion layer on the EUV reticle carrier assembly, depositing at least one EUV absorber layer on the EUV reticle carrier assembly and depositing a stress-relieving layer on EUV reticle carrier assembly. The coated EUV reticle carrier assemblies exhibit reduced particle defect generation during EUV mask blank manufacturing.

Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in an organic light-emitting diode (OLED) display are described herein. The overhang structures are permanent to the sub-pixel circuit. The overhang structures include a conductive oxide. A first configuration of the overhang structures includes a base portion and a top portion with the top portion disposed on the base portion. In a first sub-configuration, the base portion includes the conductive oxide of at least one of a TCO material or a TMO material. In a second sub-configuration, the base portion includes a metal alloy material and the conductive oxide of a metal oxide surface. A second configuration of the overhang structures includes the base portion and the top portion with a body portion disposed between the base portion and the top portion. The body portion includes the metal alloy body and the metal oxide surface.

Abstract: Exemplary methods of forming a semiconductor structure may include forming a liner along sidewalls of a trench defined from a first surface of a semiconductor substrate. The liner may extend along the first surface of the semiconductor substrate. The methods may include filling the trench with a dielectric material. The methods may include removing the dielectric material and the liner from the first surface of the semiconductor substrate. The methods may include forming a layer of the liner across the first surface of the semiconductor substrate and the trench defined within the semiconductor substrate.

Abstract: Methods of producing grating materials with variable height fins are provided. In one example, a method may include providing a mask layer atop a substrate, the mask layer including a first opening over a first processing area and a second opening over a second processing area. The method may further include etching the substrate to recess the first and second processing areas, forming a grating material over the substrate, and etching the grating material in the first and second processing areas to form a plurality of structures oriented at a non-zero angle with respect to a vertical extending from a top surface of the substrate.

Abstract: The disclosure describes devices, systems, and methods for causing a factory interface of an electronic device manufacturing system to be moveable between a first position and a second position. An electronic device manufacturing system can include a transfer chamber, processing chambers connected to the transfer chamber, a load lock connected to the transfer chamber, and a factory interface connected to the load lock. The factory interface can be moveable between a first position and a second position. The factory interface, while oriented in the first position, is positioned for transfer of one or more substrates between the factory interface and the load lock, where at least one of the transfer chamber or the load lock are inaccessible for maintenance while the factory interface is oriented at the first position. The factory interface, while oriented in the second position, is positioned to provide maintenance access to at least one of the transfer chamber or the load lock.

Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.

Abstract: Some implementations of a retaining ring has an inner surface having a first portion formed of multiple planar facets and a second portion that adjoins the first portion along a boundary and includes a frustoconical surface that is sloped downwardly from outside in. Some implementations of the retaining ring have a crenellated or serpentine inner surface, and/or an inner surface with alternating region of different surface properties or different tilt angles.

Abstract: The systems and methods discussed herein are associated with substrate support pedestals used in processing chambers to manufacture semiconductors, electronics, optics, and other devices. The substrate support pedestals include an electrostatic chuck body bonded to a cooling base via a bond layer. A gas flow passage is formed between a top surface of the electrostatic chuck body and a bottom surface of the cooling base, and a porous plug is positioned in the gas flow passage. The gas flow passage passes through a hole in the bond layer and the porous plug and has a swept volume physically shielded from an inside edge of the hole in the bond layer, protecting the bond layer from erosion.

Abstract: Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include providing a patterned hardmask over a substrate, and providing, from an ion source, a plasma treatment to a first section of the patterned hardmask, wherein a second section of the patterned hardmask does not receive the plasma treatment. The method may further include etching the substrate to form a plurality of fins in the substrate, wherein the first section of the patterned hardmask is etched faster than the second section of the patterned hardmask.