Abstract: Process kits, processing chambers, and methods for processing a substrate are provided. The process kit includes an edge ring, a sliding ring, an adjustable tuning ring, and an actuating mechanism. The edge ring has a first ring component interfaced with a second ring component that is movable relative to the first ring component forming a gap therebetween. The sliding ring is positioned beneath the edge ring. The adjustable tuning ring is positioned beneath the sliding ring. The actuating mechanism is interfaced with the lower surface of the adjustable tuning ring and configured to actuate the adjustable tuning ring such that the gap between the first and second ring components is varied. In one or more examples, the sliding ring includes a matrix and a coating, the matrix contains an electrically conductive material and the coating contains an electrically insulting material.
Abstract: An apparatus may include a main chamber, the main chamber comprising a plurality of electrodes; an entrance tunnel, the entrance tunnel having an entrance axis extending into the main chamber along a first direction; and an exit tunnel, connected to the main chamber and defining an exit axis, wherein the entrance axis and the exit axis define a beam bend of at least 30 degrees therebetween.
Type:
Grant
Filed:
November 20, 2018
Date of Patent:
September 29, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Alexandre Likhanskii, Frank Sinclair, Shengwu Chang
Abstract: An external magnetic filter to trap electrons surrounds a reactor chamber and has multiple magnets arranged in a circle, the magnetic orientation of each individual magnet being rotated relative to the orientation of the adjacent individual magnet by a difference angle that is a function of the arc subtended by the individual magnet.
Type:
Grant
Filed:
August 21, 2015
Date of Patent:
September 22, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Kartik Ramaswamy, Kenneth S. Collins, Steven Lane, Yang Yang, Lawrence Wong
Abstract: Methods of forming self-aligned patterns are described. A film material is deposited on a patterned film to fill and cover features formed by the patterned film. The film material is recessed to a level below the top of the patterned film. The recessed film is converted to a metal film by exposure to a metal precursor followed by volumetric expansion of the metal film.
Abstract: A method and apparatus for de-chucking a workpiece is described that uses a swing voltage sequence. One example pertains to a method that includes applying a mechanical force from an electrostatic chuck against the back side of a workpiece that is electrostatically clamped to the chuck, applying a sequence of voltage pulses with a same polarity to the electrodes, each pulse of the sequence having a lower voltage than the preceding pulse, each pulse of the sequence having a lower voltage than the preceding pulse, and determining whether the workpiece is released from the chuck after the sequence of additional voltage pulses and if the workpiece is not released then repeating applying the sequence of voltage pulses.
Abstract: An additive manufacturing apparatus for forming a part includes a support, a first dispenser to deliver a layer of first particles on a support or an underlying layer on the support, a second dispenser to deliver second particles onto the layer of first particles such that the second particles infiltrate into the layer of first particles, an energy source to fuse the first particle and second particles to form a fused layer of the part, and a controller coupled to the first dispenser, second dispenser and energy source.
Type:
Grant
Filed:
June 17, 2016
Date of Patent:
September 22, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Hou T. Ng, Nag B. Patibandla, Ajey M. Joshi, Ashavani Kumar, Kasiraman Krishnan
Abstract: Described are doped TaN films, as well as methods for providing the doped TaN films. Doping TaN films with Ru, Cu, Co, Mn, Al, Mg, Cr, Nb, Ti and/or V allows for enhanced copper barrier properties of the TaN films. Also described are methods of providing films with a first layer comprising doped TaN and a second layer comprising one or more of Ru and Co, with optional doping of the second layer.
Type:
Grant
Filed:
November 30, 2012
Date of Patent:
September 22, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Annamalai Lakshmanan, Paul F. Ma, Mei Chang, Jennifer Shan
Abstract: Embodiments of the disclosure include an electrostatic chuck assembly, a processing chamber and a method of maintaining a temperature of a substrate is provided. In one embodiment, an electrostatic chuck assembly is provided that includes an electrostatic chuck, a cooling plate and a gas box. The cooling plate includes a gas channel formed therein. The gas box is operable to control a flow of cooling gas through the gas channel.
Type:
Grant
Filed:
December 11, 2014
Date of Patent:
September 22, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Brian T. West, Manoj A. Gajendra, Soundarrajan Jembulingam
Abstract: An apparatus and method are provided for controlling the intensity and distribution of a plasma discharge in a plasma chamber. In one embodiment, a shaped electrode is embedded in a substrate support to provide an electric field with radial and axial components inside the chamber. In another embodiment, the face plate electrode of the showerhead assembly is divided into zones by isolators, enabling different voltages to be applied to the different zones. Additionally, one or more electrodes may be embedded in the chamber side walls.
Type:
Grant
Filed:
November 24, 2014
Date of Patent:
September 15, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Karthik Janakiraman, Thomas Nowak, Juan Carlos Rocha-Alvarez, Mark A. Fodor, Dale R. Du Bois, Amit Bansal, Mohamad Ayoub, Eller Y. Juco, Visweswaren Sivaramakrishnan, Hichem M'Saad
Abstract: Disclosed are methods for reducing transfer pattern defects in a semiconductor device. In some embodiments, a method includes providing a semiconductor device including a plurality of photoresist lines on a stack of layers, wherein the plurality of photoresist lines includes a bridge defect extending between two or more photoresist lines of the plurality of photoresist lines. The method may further include forming a plurality of mask lines by etching a set of trenches in a first layer of the stack of layers, and removing the bridge defect by etching the bridge defect at a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the stack of layers.
Type:
Grant
Filed:
June 21, 2019
Date of Patent:
September 15, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Regina Freed, Steven R. Sherman, Nadine Alexis, Lin Zhou
Abstract: An article comprises a body having a coating. The coating comprising a eutectic system having a super-lattice of a first fluoride and a second fluoride. The coating includes a glaze on a surface of the coating, the glaze comprising the eutectic system having the super-lattice of the first fluoride and the second fluoride.
Abstract: Embodiments of the present disclosure generally relate to expandable substrate inspection systems. The inspection system includes multiple metrology units adapted to inspect, detect, or measure one or more characteristics of a substrate, including thickness, resistivity, saw marks, geometry, stains, chips, micro cracks, and crystal fraction. The inspection systems may be utilized to identify defects on substrates and estimate cell efficiency prior to processing a substrate. Substrates may be transferred through the inspection system and/or between metrology units on a track or conveyor, and then sorted via at least one gripper coupled with the high speed rotatory sorting apparatus into respective bins based upon the inspection data. The rotary sorting apparatus maintains a sorting capability of at least 5,400 substrates per hour. Each bin may optionally have a gas support cushion for supporting the substrate as it falls from the rotary sorting apparatus into the respective bin.
Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.
Type:
Grant
Filed:
April 24, 2017
Date of Patent:
September 15, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Shiyu Sun, Nam Sung Kim, Bingxi Sun Wood, Naomi Yoshida, Sheng-Chin Kung, Miao Jin
Abstract: A chamber component for a processing chamber is disclosed herein. In one embodiment, a chamber component for a processing chamber includes a component part body having unitary monolithic construction. The component part body has a textured surface. The textured surface includes a plurality of independent engineered macro features integrally formed with the component part body. The engineered macro features include a macro feature body extending from the textured surface.
Type:
Grant
Filed:
February 4, 2016
Date of Patent:
September 15, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Kadthala R. Narendrnath, Govinda Raj, Goichi Yoshidome, Bopanna Ichettira Vasantha, Umesh M. Kelkar
Abstract: Optical grating components and methods of forming are provided. In some embodiments, a method includes providing an optical grating layer, and forming an optical grating in the optical grating layer, wherein the optical grating comprises a plurality of angled trenches disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the optical grating layer. The method may further include delivering light from a light source into the optical grating layer, and measuring at least one of: an undiffracted portion of the light exiting the optical grating layer, and a diffracted portion of the light exiting the optical grating layer.
Type:
Grant
Filed:
January 4, 2019
Date of Patent:
September 15, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Joseph C. Olson, Ludovic Godet, Rutger Meyer Timmerman Thijssen, Morgan Evans
Abstract: Implementations of the present disclosure generally relate to methods for cleaning processing chambers. More specifically, implementations described herein relate to methods for determining processing chamber cleaning endpoints. In some implementations, a “virtual sensor” for detecting a cleaning endpoint is provided. The “virtual sensor” is based on monitoring trends of chamber foreline pressure during cleaning of the chamber, which involves converting solid deposited films on the chamber parts into gaseous byproducts by reaction with etchants like fluorine plasma for example. Validity of the “virtual sensor” has been confirmed by comparing the “virtual sensor” response with infrared-based optical measurements. In another implementation, methods of accounting for foreline pressure differences due to facility design and foreline clogging over time.
Type:
Grant
Filed:
November 13, 2017
Date of Patent:
September 15, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Hemant P. Mungekar, William Pryor, Zhijun Jiang
Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
Type:
Application
Filed:
February 28, 2020
Publication date:
September 10, 2020
Applicant:
Applied Materials, Inc.
Inventors:
Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
Abstract: A gas flow is described to reduce condensation with a substrate processing chuck. In one example, a workpiece holder in the chamber having a puck to carry the workpiece for fabrication processes, a top plate thermally coupled to the puck, a cooling plate fastened to and thermally coupled to the top plate, the cooling plate having a cooling channel to carry a heat transfer fluid to transfer heat from the cooling plate, a base plate fastened to the cooling plate opposite the puck, and a dry gas inlet of the base plate to supply a dry gas under pressure to a space between the base plate and the cooling plate to drive ambient air from between the base plate and the cooling plate.
Abstract: A computer implemented method of monitoring a polishing process includes, for each sweep of a plurality of sweeps of an optical sensor across a substrate undergoing polishing, obtaining a plurality of current spectra, each current spectrum of the plurality of current spectra being a spectrum resulting from reflection of white light from the substrate, for each sweep of the plurality of sweeps, determining a difference between each current spectrum and each reference spectrum of a plurality of reference spectra to generate a plurality of differences, for each sweep of the plurality of sweeps, determining a smallest difference of the plurality of differences, thus generating a sequence of smallest difference, and determining a polishing endpoint based on the sequence of smallest differences.
Type:
Grant
Filed:
July 2, 2014
Date of Patent:
September 8, 2020
Assignee:
Applied Materials, Inc.
Inventors:
Boguslaw A. Swedek, Dominic J. Benvegnu, Jeffrey Drue David
Abstract: Embodiments presented herein provide techniques for planning and scheduling in a factory. The technique begins by generating a bottleneck loading plan from a plurality of inputs. A simulation is run using the bottleneck loading plan. The factory is simulated using decisions made based on the bottleneck loading plan and a lot-to-machine schedule is generated with the simulation bottleneck loading plan.