Abstract: A method and apparatus for growing an oxide layer within a feature of a substrate is described herein. The method is suitable for use in semiconductor manufacturing. The oxide layer is formed by exposing a substrate to both a high pressure oxidant exposure and a lower pressure oxygen containing plasma exposure. The high pressure oxidant exposure is performed at a pressure of greater than 10 Torr, while the lower pressure oxygen containing plasma exposure is performed at a pressure of less than about 10 Torr. The features are high-aspect ratio trenches or holes within a stack of silicon oxide and silicon nitride layers.

Abstract: A neural network is trained for use in a substrate residue classification system by obtaining ground truth residue level measurements of a top layer of a calibration substrate at a plurality of locations, each location at a defined position for a die being fabricated on the substrate. A plurality of color images of the calibration substrate are obtained, each color image corresponding to a region for a die being fabricated on the substrate. A neural network is trained to convert color images of die regions from an in-line substrate imager to residue level measurements for the top layer in the die region.

Abstract: There is provided a system of examination of a semiconductor specimen, comprising a processor and memory circuitry configured to obtain, for each given candidate defect of a plurality of candidate defects in an image of the specimen, a given area of the given candidate defect in the image, obtain a reference image, perform a segmentation of at least part of the reference image, to determine, for each given candidate defect, first reference areas in the reference image matching a given reference area corresponding to the given area, select among the first reference areas, a plurality of second reference areas, obtain a plurality of corresponding second areas in the image, and use data informative of a pixel intensity of the second areas and data informative of a pixel intensity of the given area to determine whether the given candidate defect corresponds to a defect.

Abstract: An advanced temperature control system and method are described for a wafer carrier in a plasma processing chamber. In one example a heat exchanger provides a temperature controlled thermal fluid to a fluid channel of a workpiece carrier and receives the thermal fluid from the fluid channel. A proportional valve is between the heat exchanger and the fluid channel to control the rate of flow of thermal fluid from the heat exchanger to the fluid channel. A pneumatic valve is also between the heat exchanger and the fluid channel also to control the rate of flow of thermal fluid from the heat exchanger and the fluid channel. A temperature controller receives a measured temperature from a thermal sensor of the carrier and controls the proportional valve and the pneumatic valve in response to the measured temperature to adjust the rate of flow of the thermal fluid.

Abstract: Embodiments of the present disclosure generally relate to inductively coupled plasma sources and plasma processing apparatus. In at least one embodiment, plasma source includes a first sidewall and a gas injection insert defining a plasma source interior volume. The gas injection insert includes a peripheral gas injection port, a second sidewall disposed concentric with the first sidewall, and a center gas injection port. The plasma source includes a first induction coil disposed proximate the first sidewall and disposed around the first sidewall. The plasma source includes a first radio frequency power generator coupled with the first induction coil. The plasma source includes a second induction coil disposed proximate the second sidewall and disposed around the second sidewall. The plasma source includes a second radio frequency power generator coupled with the second induction coil.

Abstract: An electronic device manufacturing system includes a mainframe including a transfer chamber and facets defining side walls of the transfer chamber. The facets include first facet, second facet, third facet, and fourth facet that form the transfer chamber. The first facet has a first number of substrate access ports. The second facet has a second number of substrate access ports. A first substrate access port of the first facet has a first side dimension and a second substrate access port of the second facet has a second side dimension that is different from the first side dimension. The second facet is adjacent to the first facet. The third facet is adjacent to the second facet. The fourth facet has the second number of substrate access ports. The second number of substrate access ports is different than the first number of substrate access ports.

Abstract: Exemplary etching methods may include modifying an exposed surface of a layer of metal oxide on a substrate housed in a processing region of a semiconductor processing chamber to produce a modified portion of metal oxide. The methods may include contacting the modified portion of metal oxide with a fluorine-containing precursor. The contacting may produce a metal oxy-fluoride material. The methods may include flowing an etchant precursor into the processing region. The methods may include contacting the metal oxy-fluoride material with the etchant precursor. The methods may include removing the metal oxy-fluoride material.

Abstract: An apparatus for contactless transportation of a carrier is provided. The apparatus includes the carrier, being a substrate carrier or a mask carrier. The apparatus includes a linear reluctance motor for providing both a contactless levitation and a contactless drive of the carrier. The linear reluctance motor includes one or more linear stators defining a transportation track for the carrier. The linear reluctance motor includes a mover attached to the carrier. The linear reluctance motor includes a set of electromagnets and a first magnetic material. The one or more linear stators include the set of electromagnets and the mover includes the first magnetic material, or the mover includes the set of electromagnets and the one or more linear stators include the first magnetic material. The apparatus includes a controller connected to the set of electromagnets.

Abstract: An apparatus for contactless transportation of a carrier is provided. The apparatus includes the carrier, being a substrate carrier or a mask carrier. The apparatus includes a linear reluctance motor for providing both a contactless levitation and a contactless drive of the carrier. The linear reluctance motor includes one or more linear stators defining a transportation track for the carrier. The linear reluctance motor includes a mover attached to the carrier. The linear reluctance motor includes a set of electromagnets and a first magnetic material. The one or more linear stators include the set of electromagnets and the mover includes the first magnetic material, or the mover includes the set of electromagnets and the one or more linear stators include the first magnetic material. The apparatus includes a controller connected to the set of electromagnets.

Abstract: A wideband variable impedance load for high volume manufacturing qualification and diagnostic testing of a radio frequency power source, an impedance matching network and RF sensors for generating plasma in a semiconductor plasma chamber for semiconductor fabrication processes. The wideband variable impedance load may comprise a fixed value resistance operable at a plurality of frequencies and coupled with a variable impedance network capable of transforming the fixed value resistance into a wide range of complex impedances at the plurality of frequencies. Response times and match tuning element position repeatability may be verified. Automatic testing, verification and qualification of production and field installed radio frequency power sources for plasma generation are easily performed.

Abstract: Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A first layer of silicon-and-germanium-containing material, a second layer of silicon-and-germanium-containing material, and a layer of silicon-containing material may be disposed on the substrate. The methods may include contacting the substrate with the oxygen-containing precursor. The contacting may oxidize at least a portion of the second layer of silicon-and-germanium-containing material. The methods may include providing a first etchant precursor to the processing region and contacting the substrate with the first etchant precursor. The contacting may selectively etch the first layer of silicon-and-germanium-containing material. The methods may include providing a second etchant precursor to the processing region.

Abstract: Exemplary semiconductor processing methods may include a substrate housed in the processing region. A layer of silicon-containing material may be disposed on the substrate, a patterned resist material may be disposed on the layer of silicon-containing material, and a layer of carbon-containing material may be disposed on the patterned resist material and the layer of silicon-containing material. The methods may include providing a hydrogen-containing precursor, a nitrogen-containing precursor, or both to a processing region of a semiconductor processing chamber, forming plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor, and contacting the substrate with the plasma effluents of the hydrogen-containing precursor and/or the nitrogen-containing precursor. The contacting may remove a portion of the layer of carbon-containing material.

Abstract: Embodiments of the present disclosure generally relate to a lift pin guide. The lift pin guide includes a cylindrical main section, a flange, a cylindrical recess, a cylindrical extension, and a bore. The flange is disposed at a first end of the cylindrical main section and has a diameter greater than a diameter of the cylindrical main section. The cylindrical recess is formed in a first surface of the flange, the first surface of the flange being opposite the cylindrical main section, and the cylindrical recess having an outer diameter less than the diameter of the cylindrical main section. The cylindrical extension protrudes beyond the first surface of the flange, the cylindrical extension being concentric with the cylindrical main section. The bore is formed through the cylindrical main section and the cylindrical extension.

Abstract: A Chemical Mechanical Polishing (CMP) process may generally apply more pressure around a periphery of the polishing pad than at the center of the polishing pad. This may cause uneven material removal as the substrate moves along the surface of the polishing pad. Therefore, the polishing pad may include one or more recesses around a periphery of the polishing pad to relieve pressure on the substrate. The one or more recesses may be connected to channels that extend radially outward from the recesses to the edge of the polishing pad. The recesses may collect polishing slurry during the CMP process and direct the slurry into the channels. The channels may then expel the collected polishing slurry off of the polishing pad to clear the recesses.

Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

Abstract: Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate including one or more features may be housed within the processing region. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming plasma effluents of the silicon-containing precursor and the hydrogen-containing precursor. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend into the one or more features.

Abstract: Disclosed herein are methods for forming opening ends within semiconductor structures. In some embodiments, a method may include providing an opening formed in a layer of a semiconductor device, wherein the opening comprises a set of sidewalls opposite one another, and first and second end walls connected to the sidewalls, wherein each of the first and second end walls defines a tip end and a set of curved sections extending between the tip end and the set of sidewall. The method may further include performing an ion etch to the opening by delivering an ion beam at a non-zero angle relative to a plane defined by the layer of the semiconductor device, wherein the ion etch comprises a lean-gas chemistry, and wherein the ion etch causes the layer of the semiconductor device to be removed faster along the set of curved sections than along the set of sidewalls.

Abstract: Exemplary semiconductor processing methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber. The methods may include flowing a boron-containing precursor into the substrate processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-silicon-containing layer on a substrate in the substrate processing region of the semiconductor processing chamber. The boron-and-silicon-containing layer may be characterized by an increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer opposite the first surface. A flow rate of the boron-containing precursor may be increased during the deposition of the boron-and-silicon-containing layer.

Abstract: Exemplary semiconductor processing methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-nitrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors. The methods may include depositing a layer of silicon-carbon-and-nitrogen-containing material on the substrate. The layer of silicon-carbon-and-nitrogen-containing material may be characterized by a dielectric constant of less than or about 4.0. The layer of silicon-carbon-and-nitrogen-containing material may be characterized by a leakage current at 2 MV/cm of less than or about 3E-08 A/cm2.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices, fin field effect transistors (FinFETs) in particular, and methods of manufacturing such devices having improved effective capacitance (Ceff). The FinFETs include a gate structure in which airgaps are provided by recessing a high-k material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high-k dielectric layer and improving effective capacitance (Ceff) of the device.