Abstract: A substrate is disposed within a processing chamber. A nitrogen precursor and a group-III precursor are flowed into the processing chamber. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process at an elevated temperature within the processing chamber using the nitrogen precursor and the group-III precursor. Light beams are directed to a surface of the layer and light spots corresponding to reflections of the light beams are received from the surface at a position-sensitive detector. Positions of the light spots on the position-sensitive detector are determined from photocurrent induced in a photodiode in the position-sensitive detector. A curvature of the layer is determined from the positions of the light spots.

Abstract: A method for fabricating a multiple layer silicon nitride film on a semiconductor substrate is provided herein. In one embodiment, a method for fabricating a multiple layer silicon nitride film on a semiconductor substrate includes providing a substrate over which the multiple layer silicon nitride film is to be formed; and forming the multiple layer silicon nitride film in a single processing reactor by: (a) depositing a base layer comprising silicon nitride on the base structure; (b) depositing a middle layer comprising a stress-controlling material on the base layer; and (c) depositing a top layer comprising silicon nitride on the middle layer. The stress-controlling material selectively increases or reduces the stress of the multiple layer silicon nitride film as compared to silicon nitride alone.

Abstract: Embodiments are provided for a method to deposit barrier and tungsten materials on a substrate. In one embodiment, a method provides forming a barrier layer on a substrate and exposing the substrate to a silane gas to form a thin silicon-containing layer on the barrier layer during a soak process. The method further provides depositing a tungsten nucleation layer over the barrier layer and the thin silicon-containing layer during an atomic layer deposition process and depositing a tungsten bulk layer on the tungsten nucleation layer during a chemical vapor deposition process. In some examples, the barrier layer contains metallic cobalt and cobalt silicide, or metallic nickel and nickel silicide. In other examples, the barrier layer contains metallic titanium and titanium nitride, or metallic tantalum and tantalum nitride.

Abstract: A system and method of determining shape and position corrections of a beam such as a particle or other beam used in a system such as a particle beam lithography. The method of providing corrected deflector voltages may include determining a voltage step value by subtracting a previous deflector voltage value with a current deflector voltage value; determining a plurality of correction values using the voltage step value and an exposure time for the current deflector voltage value; selecting a current voltage correction value from the plurality of correction values using the current deflector voltage value; and calculating a corrected deflector voltage value by adding the current voltage correction value to the current deflector voltage value.

Abstract: A multilayer antireflective hard mask structure is disclosed. The structure comprises: (a) a CVD organic layer, wherein the CVD organic layer comprises carbon and hydrogen; and (b) a dielectric layer over the CVD organic layer. The dielectric layer is preferably a silicon oxynitride layer, while the CVD organic layer preferably comprises 70-80% carbon, 10-20% hydrogen and 5-15% nitrogen. Also disclosed are methods of forming and trimming such a multilayer antireflective hard mask structure. Further disclosed are methods of etching a substrate structure using a mask structure that contains a CVD organic layer and optionally has a dielectric layer over the CVD organic layer.

Abstract: Embodiments of substrate heating methods and apparatus are provided herein. In one embodiment, a substrate heater is provided including a heater plate having a top surface and an opposing bottom surface, a recess formed in the top surface, the recess having a feature having an upper surface for supporting a substrate, wherein the depth from a bottom surface of the recess to the upper surface of the feature is at least 5 mils. One or more pads may be disposed in the recess for supporting a substrate. The heater plate may have a thickness of about 19 mm. One or more indentations may be formed in the bottom surface of the recess for altering the rate of heat transfer to a portion of a substrate disposed above the indentation during processing. The heater plate may be utilized in a process chamber for performing heat-assisted processes.

Abstract: Embodiments of the present invention are directed to adjusting the spacing between the substrate support and the faceplate of the gas distribution member to achieve improved uniformity of the layer formed on the substrate. One embodiment of the present invention is directed to a method of adjusting a spacing between a gas distribution member and a substrate support disposed generally opposite from the gas distribution member, wherein the substrate support is configured to support a substrate on which to form a layer with improved thickness uniformity. The method comprises forming a layer on the substrate disposed on the substrate support; measuring a thickness of the layer on the substrate; and calculating differences in thickness between a reference location on the substrate and a plurality of remaining locations on the substrate.

Abstract: Apparatus and methods of thermally treating a wafer or other substrate, such as rapid thermal processing (RTP) apparatus and methods are disclosed. An array of radiant lamps directs radiation to the back side of a wafer to heat the wafer. In one or more embodiments, the front side of the wafer on which the patterned integrated circuits are being formed faces a radiant reflector. In one or more embodiments, the wafer is thermally monitored for temperature and reflectivity from the side of the reflector.

Abstract: The invention relates to a measuring device for measuring the degree of transmission of a coating on a glass plate. The glass plate rests on a support relative to which it is shifted. The support is provided with a gap enabling a light beam to pass through the glass plate and to impinge on a light receiver. Thus, the degree of transmission of the coating can be determined. Further, the reflection and the electric resistance of the coating can be measured by the measuring device.

Abstract: Methods are provided for depositing materials in forming semiconductor devices on a substrate, such as metal oxide transistors. In one embodiment, the invention generally provides a method of processing a substrate including forming a gate dielectric on a substrate having a first conductivity, forming a gate electrode on the gate dielectric, forming a first pair of sidewall spacers along laterally opposite sidewalls of the gate electrode, etching a pair of source/drain region definitions on opposite sides of the electrode, depositing a silicon-germanium material selectively in the source/drain region definitions, and implanting a dopant in the deposited silicon-germanium material to form a source/drain region having a second conductivity.

Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).

Abstract: The present invention provides methods and apparatus for controlling the quantity of fluid output (e.g., drop size) by individual nozzles of a print head to a very high precision at a frequency equal to the frequency at which fluid is normally dispensed. This is achieved by mapping fluid quantity control information into the data that represents the image to be printed. Data representative of an image is received and converted into pixel data. In at least one embodiment, the pixel data includes pixels represented by N bits, and the N bits may represent a drop size for the pixel and a union of the N bits may represent a nozzle status. A print head may be controlled based on the pixel data, and the print head may include nozzles that are each adapted to deposit at least one drop size quantity of a fluid on a substrate.

Abstract: The invention relates to an energy and media connection module for coating installations. Said module serves for supplying with cooling water, compressed air, process gases, signal, control and cathode power. It can be moved from one coating chamber to another coating chamber along a coating line by a single person in a short time. Further, it is possible to separate the energy connection module from a coating chamber for maintenance or displacement purposes without mechanically demounting all connections.

Abstract: A method, apparatus and medium of conditioning a planarizing surface includes installing a wafer to be polished in a chemical mechanical polishing (CMP) apparatus having a polishing pad and a conditioning disk, polishing the wafer under a first set of pad conditioning parameters selected to maintain wafer material removal rates with preselected minimum and maximum removal rates, determining a wafer material removal rate occurring during the polishing step, calculating updated pad conditioning parameters to maintain wafer material removal rates within the maximum and minimum removal rates, and conditioning the polishing pad using the updated pad conditioning parameters, wherein the updated pad conditioning parameters are calculated using a pad wear and conditioning model that predicts the wafer material removal rate of the polishing pad based upon pad conditioning parameters, such as the conditioning down force and rotational speed of the conditioning disk.

Abstract: In a first aspect, a first method is provided for electronic device manufacturing. The first method includes the steps of (1) receiving a request to transfer a carrier from a first substrate loading station to a second substrate loading station of an electronic device manufacturing facility including a plurality of substrate loading stations, wherein the facility further includes a plurality of carrier supports coupled to a conveyor system adapted to move the carrier within the facility; (2) assigning one of the plurality of carrier supports to transfer the carrier from the first substrate loading station to the second substrate loading station such that at least one of a time required for the transfer is reduced and balance of the conveyor system is maintained; (3) moving the carrier from the first substrate loading station; and (4) moving the carrier to the second substrate loading station. Numerous other aspects are provided.

Abstract: An improved deposition chamber (2) includes a housing (4) defining a chamber (18) which houses a substrate support (14). A mixture of oxygen and SiF4 is delivered through a set of first nozzles (34) and silane is delivered through a set of second nozzles (34a) into the chamber around the periphery (40) of the substrate support. Silane (or a mixture of silane and SiF4) and oxygen are separately injected into the chamber generally centrally above the substrate from orifices (64, 76). The uniform dispersal of the gases coupled with the use of optimal flow rates for each gas results in uniformly low (under 3.4) dielectric constant across the film.

Abstract: The invention relates to a magnetron with a planar target and a planar magnet system. The planar magnet system comprises a bar-shaped first magnet pole with enlarged ends and a frame-shaped second magnet pole, wherein a relative movement between the magnet poles and the target is such that every point of the magnet system moving with the target being stationary moves on a circular path. If the magnet system is stationary, each point of the target moves on such a circular path. During the relative movement with respect to one another the magnet system and the target are in parallel planes. The diameter of the circular path corresponds to the mean distance between two parallel arms of a plasma tube, which during the sputter operation develops between the first and the second magnet pole. Thereby that the magnets in the curve region of the plasma tube are disposed such that the pole lines form at this site a circle arc or a circular area, holes in the target are avoided.

Abstract: An integrated copper deposition process, particularly useful for forming a copper seed layer in a narrow via prior to electrochemical plating of copper, including at least one cycle of sputter deposition of copper followed by sputter etching of the deposited copper, preferably performed in a same sputter chamber. The deposition is performed under conditions promoting high copper ionization fractions and strong wafer biasing to draw the copper ions into the via. The etching may be done with argon ions, preferably inductively excited by an RF coil around the chamber, or by copper ions, which may be formed with high target power and intense magnetron or by use of the RF coil. Two or more cycles of deposition/etch may be performed. A final flash deposition may be performed with high copper ionization and low wafer biasing.

Abstract: A method to extend the process monitoring capabilities of a semiconductor wafer optical inspection system so as to be able to detect low-resolution effects of process variations over the surface of a wafer at much higher sensitivity than heretofore possible. The method consists, in essence, of grouping sensed pixels by geometric blocks over the inspected surface and comparing each block with a corresponding one from another die on the same wager, from another wager of from a stored model image. In one embodiment of the invention, pixel values are compared directly and differences are thresholded at a considerably lower level than during a defects detection process. In another embodiment, there is calculated a signature for each block, based on the sensed light intensity values, and corresponding signatures are compared.

Abstract: A method for depositing a low dielectric constant film by flowing a oxidizing gas into a processing chamber, flowing an organosilicon compound from a bulk storage container through a digital liquid flow meter at an organosilicon flow rate to a vaporization injection valve, vaporizing the organosilicon compound and flowing the organosilicon compound and a carrier gas into the processing chamber, maintaining the organosilicon flow rate to deposit an initiation layer, flowing a porogen compound from a bulk storage container through a digital liquid flow meter at a porogen flow rate to a vaporization injection valve, vaporizing the porogen compound and flowing the porogen compound and a carrier gas into the processing chamber, increasing the organosilicon flow rate and the porogen flow rate while depositing a transition layer, and maintaining a second organosilicon flow rate and a second porogen flow rate to deposit a porogen containing organosilicate dielectric layer.