Abstract: A graphics processing circuit includes a pixel shader operative to provide pixel color information in response to image data representing a scene to be rendered; a texture circuit, coupled to the pixel shader, operative to determine a luminance value to be applied to a pixel of interest based on the luminance values of the pixels that define a plane including the pixel of interest; and a render back end circuit, coupled to the texture circuit, operative to compute the luminance values from a shadow map that specifies the distance from the light source of the nearest object at a plurality of locations.

Abstract: An input/output circuit in a receiving mode typically has disabled output buffers as well as other electrical components that provide significant receiver input capacities at high operating frequencies. A detection circuit detects the charging/discharging of the parasitic capacitance and operates a regulating circuit to compensate for the charging/discharging of the parasitic capacitance during rising/falling edges of an input signal, thereby correcting for impedance mismatch and reflection glitches.

Abstract: The present disclosure relates to thermal management apparatus for a circuit substrate having heat generating components mounted on one or both sides thereof. The apparatus and method includes a circuit assembly having a first thermally conductive layer disposed on each side of the circuit substrate and being thermally coupled to one or more heat generating components of the circuit substrate. The apparatus and method includes a second thermally conductive layer disposed on each side of the circuit substrate and being thermally coupled to the first thermally conductive layer. The first thermally conductive layer and the thermally conductive layer can be shaped, sized, and/or configured to provide cooling of the one or more heat generating components disposed on each side of the circuit substrate by transferring and spreading the heat to the outside of the circuit assembly.

Abstract: A video processor integrates the processing of video and graphics data by restructuring the discrete blocks of luminance and chrominance component data associated with video image data (Y,U,V) into composite pixel values (YUYV), and performing the subsequent processing, in particular motion compensation, upon this composite data form. The discrete blocks of video image data are queue and processed in parallel to form a composite pixel value associated with each pixel within the image areas represented by the discrete blocks. By forming composite pixel values for reference data and error term data, common processing elements can be optimized and used for both video and graphics image processing. For example, the trilinear interpolator commonly used for 3-D graphics filtering and texturing can be used to form predicted macroblocks for motion compensation, and the specular adder used for graphics lighting effects can be used to process the motion compensation error terms.

Abstract: The present invention provides a method and apparatus for data compression that includes representing each sub-pixel of each pixel with a pointer corresponding to an attribute of the sub-pixel, the attribute being a floating point binary number. An overall attribute of each pixel is then determined. The determining of the overall attribute of each tile may include any one of assigning the attribute of the sub-pixels to the overall attribute of the pixel when the sub-pixels are represented by an identical pointer, and resolving the overall attribute of the tile by the attributes of the sub-pixels when the sub-pixels are represented by non-identical pointers of the pixel.

Abstract: A power adjustment circuit includes memory controller logic that is couplable to system memory or other memory if desired. The memory control logic is operative to provide a variable memory clock signal to the system memory and to place the system memory in a self refresh mode wherein the self refresh mode does not require a memory clock signal. Thereafter, the memory clock control logic adjusts the frequency of the memory clock signal to a lower (or higher) frequency clock signal, and in response to the frequency of the memory clock signal becoming stable, the memory clock control logic restores the memory to a normal mode using the lower adjusted frequency memory clock signal. As such, a dynamic memory clock switching mechanism is employed for quickly varying the frequency of memory modules for discrete graphics processors, graphics processors integrated on a chip, or any other processors such that the memory clock can be reduced to a lower frequency in real time to save power.

Abstract: A configurable bus interface circuit includes an internal bus bridge and an internal circuit. The configurable bus interface circuit also includes an internal I/O circuit couplable to an external circuit, via the internal bus bridge. The configurable bus interface circuit electrically isolates the internal circuit to avoid the propagation of signals between the internal I/O circuit and the external circuit.

Abstract: A multiplexed packetized data stream carrying real-time multimedia programs is received at a first hardware demultiplexer. Based on a user input, a video and timing portion of a program associated with the multiplexed packetized data stream can be stored for subsequent display. One type of subsequent display is time shifted display, where the stored portion of the program is played back while new portions of the program are being stored. During time shifted play back, a second hardware demultiplexer can be used, so that one demultiplexer stores new data and maintains a current clock value while the other decodes and displays the stored data.

Abstract: A method for the production of inorganic aluminum substances and amorphous silica from aluminum oxide containing ores, comprising: (a) leaching of said ores with fluorosilicic acid to obtain aluminum fluosilicate solution; (b) filtering said leached solution from insoluble materials; and (c) washing said insoluble materials.

Abstract: A secondary representative Z value memory includes a reduced-resolution representation of a primary representative Z value memory. Upon updating of a block of the primary representative Z value memory, one or more corresponding values are calculated for updating the reduced-resolution representation.

Abstract: When a stream of packets (e.g. MPEG-2 transport stream) includes certain packets representing unscrambled digital television program content and certain other packets representing the content of a scrambled digital television program that is currently tuned by a receiver, interception of the unscrambled digital television program at an output of the receiver may be prevented by determining whether packets representing program content have an ascertained characteristic (e.g. have a packet ID matching one of a set of packet IDs) that uniquely identifies the packets as representing content of the scrambled program. For packets not having the characteristic, delivery to the output of the digital television receiver in an unscrambled state may be prevented, e.g., by discarding the packet or by overwriting its payload.

Abstract: A method and systems are provided for creating an authentication of secure communications between a software video driver and a video display. A video driver transmitting digital video data deemed high-bandwidth digital content, to a display, can perform authentication to determine if a secure connection has been established with a display. The video driver and the display both generate secret keys which are compared to ensure that the display used is authorized for secure communications. The video driver, communicating with a hardware video controller over a peripheral component interconnect (PCI) bus, can establish an encrypted link with the video driver. The video driver occasionally monitors the display to determine if a secure communications link is upheld. If the connection is determined at any time to be insecure, the video controller can alert the video driver, so that transmission of the video data can be terminated.

Abstract: A video compression algorithm for converting a digital video stream having video content into a compressed video bitstream, includes rate control to control the size of the compressed video bitstream. The rate control takes into account two or more of (1) detected scene changes, (2) detected repeated fields resulting from inverse telecine processing, (3) characterized video content complexity, and (4) a determined level of a model of a bit buffer associated with a decoder adapted to decode the compressed video bitstream. In preferred embodiments, the rate control takes into account two or more of these four factors in an integrated manner to change the allocation of bits for encoding different portions of the video stream.

Abstract: A lightweight armor with repeat hit capability includes at least one layer of material that absorbs energy upon being impacted by an object through a reversible phase change and/or an elastic strain deformation of at least 5%. Once the energy of the object has been absorbed the layer of material returns to its original shape, thereby resulting in an armor with repeat hit capabilities. The armor may also include additional layers of material constructed of conventional armor materials. A method of manufacturing such an armor is also disclosed.

Abstract: Methods and apparatus for updating a memory address remapping table using a graphics processing circuitry are disclosed. The methods include assembling a command sequence of commands executable by the graphics processing circuit, the sequence configured to include one or more memory address remapping table updates for one or more page entries in a memory address remapping table. The command sequence is then communicated to the graphics processing circuit for execution by the graphics processing circuit. Execution of the command sequence with the graphics processing circuit includes executing the one or more memory address remapping table updates causing the graphics processing circuit to update the one or more page entries in the memory address remapping table.

Abstract: A tuning module in a multi-tuner receiver stores channel parameters for tuning of channels within a channel list. Channels are tuned sequentially by the tuning module in response to channel advance (up/down) signals. Such signals may be provided by a central processor/controller. If a channel advance signal would cause the tuning module to advance past the beginning or end of the channel list, the module generates a list complete signal. The processor/controller may react accordingly. For example, the central processor/controller may disable a currently active tuning module and enable another tuning module/tuner in response to the list complete signal.

Abstract: The present disclosure relates to methods and apparatus for controlling power consumption of a plug-in card or circuit module. The disclosed method, in particular, controls power to a circuit module and includes implementing a user interface and power manager to automatically control the power state of the circuit module by, among other things, powering the module up or down using a simulated hot unplug of the device. The apparatus further includes use of an I/O interconnect to allow the system BIOS to simulate the hot unplugging of the module.

Abstract: A system and method for localization of sounds in 3-D space using Head Related Transfer Functions (HRTFs) are disclosed herein. A plurality of audio signals and/or sound sources, or “voices”, represented by data, such as one or more audio files or streaming audio data, is transmitted from an audio source, such as a compact disc player, to an audio processing system. The audio processing system, in one embodiment, prioritizes the voices based on characteristics of the voices, such as the relative listening benefit of sound localization of a particular voice. In one embodiment, a finite impulse response (FIR) filter is used to apply a HRTF to the voices. The audio processing system distributes up to a fixed number of coefficients among the voices, where the distribution of the coefficients, in one embodiment, is based on the priority of each channel. Those voices having a higher priority than other voices could have a greater number of coefficients assigned to them than the lower priority voices.

Abstract: An earth working scraper for use removing and transporting earth is disclosed. The scraper includes a scraper blade for scraping earth from a ground surface, a receiving area located near the blade for receiving earth scraped from the ground surface by the blade, a rotatable axle for providing transportation of the scraper connected with respect to the blade and receiving area, and a track apparatus connected with respect to the rotatable axle. The track apparatus may include a continuous flexible track having an upper length and a ground-engaging lower length and including an inner surface, an axle wheel mountable to the rotatable axle for rotational movement therewith, the axle wheel engaging the inner surface of the flexible track along the upper length to drive the flexible track in response to rotation of the axle, and a frame for mounting the axle wheel.

Abstract: A method of producing metal fibers including melting a mixture of at least a fiber metal and a matrix metal, cooling the mixture to form a bulk matrix comprising at least a fiber phase and a matrix phase and removing at least a substantial portion of the matrix phase from the fiber phase. Additionally, the method may include deforming the bulk matrix. In certain embodiments, the fiber metal may be at least one of niobium, a niobium alloy, tantalum and a tantalum alloy and the matrix metal may be at least one of copper and a copper alloy. The substantial portion of the matrix phase may be removed, in certain embodiments, by dissolving of the matrix phase in a suitable mineral acid, such as, but not limited to, nitric acid, sulfuric acid, hydrochloric acid and phosphoric acid.