Abstract: The present invention relates to a selectable multi-performance configuration. Instead of the traditional methods of producing separate high-end and low-end graphics chips, the present invention produces processing systems in a single unit. The single unit is readily and functionally partitionable. Each partition is capable of independent operation. By using all of the partitions a high-end graphics processing system may be simulated and tested. By using a subset of the partitions, a low-end graphics processing system may be simulated on the same system without the added cost of re-design of either hardware or software.

Abstract: In accordance with the specific embodiment of the present invention, a tuner alternates between receiving a first video signal and a second video signal, such that every other frame of a specific signal is received. This is accomplished by writing to an IF1 and IF2 control register, during a vertical blanking interval. Subsequently, the video images are displayed in full motion video by interpolating the alternating frames of data not received by the tuner.

Abstract: A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address range translated by the address translation circuitry. Each entry of the table describes a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range. The table lookup circuitry retrieves a table entry corresponding to the address, and is operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer.

Abstract: A computer concurrently executes a first operating system coded in a RISC instruction set and a second operating system coded in a CISC instruction set. When an exception is raised while executing a program coded in the RISC instruction set, an execution thread may be initiated under the CISC operating system. The exception may be delivered to the initiated thread for handling by the CISC operating system.

Abstract: A method and apparatus for gamma correction in a video graphics circuit is accomplished by storing a plurality of gamma correction curves in one or more lookup tables that can be accessed using pixel display information to generate gamma-corrected data. Gamma correction selection information is provided to select which of the gamma correction curves is utilized to perform the gamma correction for a particular set of pixel data.

Abstract: The present invention relates to a rasterizer interpolator. In one embodiment, a setup unit is used to distribute graphics primitive instructions to multiple parallel rasterizers. To increase efficiency, the setup unit calculates the polygon data and checks it against one or more tiles prior to distribution. An output screen is divided into a number of regions, with a number of assignment configurations possible for various number of rasterizer pipelines. For instance, the screen is sub-divided into four regions and one of four rasterizers is granted ownership of one quarter of the screen. To reduce time spent on processing empty times, a problem in prior art implementations, the present invention reduces empty tiles by the process of coarse grain tiling. This process occurs by a series of iterations performed in parallel. Each region undergoes an iterative calculation/tiling process where coverage of the primitive is deduced at a successively more detailed level.

Abstract: A multiphase clock generating circuit includes a multiphase clock generator that produces a plurality of multiphase output signals at a first frequency and a multiphase divider with delayed reset control. The multiphase divider with delayed reset control is operatively coupled to receive the plurality of multiphase output signals at the first frequency and further operative to produce a plurality of multiphase output signals at a second frequency based on reset control information. As a result, an interface can be supplied with and switch between multiphase clock at different frequencies within a short amount of time with reduced power consumption and circuit area.

Abstract: A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system.

Abstract: A power up biasing circuit for a split power supply based circuit includes a split power supply state sensing circuit that produces a pair of complimentary control signals indicating a presence or absence of a suitable biasing power supply voltage. A pseudo power supply voltage, based on a first power supply is selected by a selector circuit for acting as a biasing voltage for one or a plurality of components to be protected during initial power up where there is an absence of a second power supply voltage, based on the pair of complimentary control signals. Once the second power supply voltage has fully ramped up to steady state, the selector circuit selects the second power supply voltage as the biasing voltage for one or a plurality of component to be protected.

Abstract: A process and reactor for chemical conversion is taught. The process allows the selective breaking of chemical bonds in a molecule by use of fast rise alternating current or fast rise pulsed direct current, each fast rise portion being selected to have a suitable voltage and frequency to break a selected chemical bond in a molecule. The reactor for carrying out such a process includes a chamber for containing the molecule and a generator for generating and applying the selected fast rise current.

Abstract: A method and apparatus for graphics rendered in a mobile device includes a command queue capable of receiving a plurality of rendering commands, a generate_event command and a wait_until command. The wait_until command corresponds to the completion of a specific operation indicated by the generate_event command. The method and apparatus further includes a direct memory access device operably coupled to the command queue, wherein the DMA device is capable of receiving a memory access command in response to the generate_event command. A memory device is capable of storing rendering information, wherein the memory device is accessible in response to the generate_event command. Furthermore, the method and apparatus includes the command queue capable of queuing the rendering commands in response to the wait_until command until the completion of the operation indicated by the generate_event command.

Abstract: The present disclosure relates to a thermal management apparatus used to manage temperature of components mounted to a circuit substrate, such as electronic or optical components. The apparatus includes a heat dissipation structure that includes at least one protrusion extending from a surface of the heat dissipation structure. A carrier structure is also included and engages with the heat dissipation structure. The carrier structure includes an aperture that receives the at least one protrusion. Additionally, the apparatus includes at least one biasing structure that is configured to allow movement of the heat dissipation structure relative to the carrier structure and provides a biasing force tending to move the heat dissipation structure and carrier structure together.

Abstract: Variable bit size run length encoding (“RLE”) is used to encode uninterrupted runs of adjacent first symbols and adjacent second symbols within a sequence that may represent an image. The symbols may be 1s and 0s. The bit size used to encode a run length for a current run is varied in dependence on the bit sized used or required to encode a run length of a previous run of the same symbol type. Further, an image to be encoded may be transformed into an image/bit sequence representing changes from line to line in the image. By so transforming the image, the correlation from run length to run length of like colours is increased, thereby improving the efficiency of the variable bit size RLE.

Abstract: Methods and apparatus for transmitting and receiving data in a memory interface are disclosed. The apparatus include a programmable transceiver having a variable duty cycle control, with the transceiver having at least one of a programmable variable duty cycle receiver and a programmable variable duty cycle transmitter. The receiver and the transmitter are both responsive to variable duty cycle control data and operate to vary a duty cycle of one of incoming and outgoing data. By providing programmability to the data duty cycle, the transceiver can optimally accommodate different memory device standards.

Abstract: A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.

Abstract: A wireless drawing command transmitting unit includes a wireless transmitter operative to transmit drawing commands associated with a master image renderer. A wireless drawing command receiving unit includes a wireless receiver operative to receive the transmitted drawing commands and generates an image for a display device using the drawing commands transmitted wirelessly. In addition, the wireless drawing command receiving unit transmits drawing command throttle data back to the wireless drawing command transmitting unit to throttle transmission of drawing commands that are sent by the drawing command transmitting unit. A method for providing wireless display of images is also disclosed.

Abstract: A method and apparatus for multiplexing data streams is provided. An earliest time and a latest time are determined for each packet of a each data stream. The packets of the data streams are multiplexed so as to meet earliest time and latest time requirements. The calculation of the earliest time and the latest time are simplified by allowing use of linear constraints rather than irregular stairstep constraints. Compensation for drift in the data streams is also provided.

Abstract: A video information recorder receives video information including multiple scenes, and associates an automatic start marker with at least one of the scenes in response to receiving user-provided begin scene information. According to one embodiment, during playback the video information recorder stops recording in response to receiving the user provided begin scene information and resumes recording in response to receiving the user provided end scene information. According to an alternative embodiment, during playback the video information recorder skips, erases or overwrites the video information between the start and stop markers. The video information recorder also associates an automatic stop marker with at least one of the scenes without user intervention in response to receiving user-provided end scene information.

Abstract: The disclosure relates to a programmable virtual memory client, that includes programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns. Additionally, the virtual memory client includes virtual memory client control logic configured to use the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device.

Abstract: The present disclosure discusses methods and apparatus for controlling the video playback in a video playback system. In particular, a method for controlling video playback includes receiving a flip call to display video data from a flip queue buffer. Processing of the video data is then initiated. Flip acknowledgement information is issued in response to receiving the flip call information and prior to completion of the processing of video data to be displayed from the flip queue buffer. By issuing flip acknowledgement information regardless of whether the processing of the video data has been completed, video flip calls can continue to be issued at a constant rate and other processing can continue without waiting, thus resulting in better and smoother video playback and economizing processing resources. Additionally, a decision whether or not to drop a particular video frame is made based on whether a flip queue buffer from a predetermined number of flip queue buffers is available.