Abstract: A system and methods are shown for generating a transport stream. An application reads a transport stream file stored in memory. The application provides access to the transport stream file to a graphics card using a multimedia peripheral port (MPP). The MPP is used to provide data from the transport stream file to a transport stream demultiplexer. The application determines a desired transmission rate from the data present between program clock references in the transport stream file. The application suspends transmissions to the transport stream demultiplexer to allow a transmission bit-rate to match the desired bit-rate. The application also suspends transmission when the receiving transport demultiplexer determines its buffers are nearly full.

Abstract: A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization. The hardware CISC instruction decoder is exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects. The CISC decoder is designed to decode a portion of an instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder. A software emulator is programmed to implement a remainder of the instruction set.

Abstract: An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel refers to all I/O pads, which collectively provide a bus interface to an external device. For example, all the I/O pads interfacing with a memory module may be grouped into a channel, and address I/O pads in a channel may be arranged into a “group.” Memory I/O pads may be grouped together into a channel since memory interface pads have input/output characteristics that may be different from those of other types of I/O pads in the chip. According to one embodiment, per-group programmable offset information provides calibration information that may be different for each group in each channel.

Abstract: A video playback circuit receives flip call information and vertical synchronization information, and in response determines a pause mode and a playback mode. Flip call information, as is known in the art, provides an indication for flipping between a front buffer and a back buffer, in order to facilitate rendering into one buffer while rasterizing out of the other buffer. Vertical synchronization information describes the completion of rasterizing an image onto a display, and often occurs at periodic intervals, e.g., 60 Hz, 100 Hz. The video playback circuit further includes a pause/playback-based frame buffer pointer information generator. The pause/playback-based frame buffer pointer information generator generates unfiltered frame buffer pointer information when in the pause mode. Otherwise, the pause/playback-based frame buffer pointer information generator generates filtered frame buffer pointer information when in the playback mode.

Abstract: A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in another array may be output at a corresponding location. A further single instruction executable by the SIMD processor, may be applied to results obtained using such a single min/max instruction, to allow such instructions to operate on two dimensional arrays.

Abstract: A SIMD processor includes an ALU having data interconnects facilitating the concurrent processing of overlapping data portions of at least one operand store. Such interconnects facilitate the calculation of shift-invariant convolutions, and sum of absolute differences between an operand in the operand store and another operand.

Abstract: The present invention provides a scheme for compressing the color components of image data. The pixel data is grouped into a plurality of tiles for storage. A test is performed to determine if a tile can be compressed so that its size after compression is less than its size before compression. If so, the tile is compressed. A tile table is provided that includes a flag that can be set for each tile that is compressed. In a data transfer from memory to a graphics processor, the tile table is examined to identify those tiles that are compressed and must be decompressed prior to use. In one embodiment, a number of compression schemes are available for use on a tile and the best compression scheme is chosen on a tile by tile basis. The invention includes an identifying code for each compression scheme (stored as a value in each compressed tile).

Abstract: A trellis decoder decodes a stream of encoded symbols, including symbols of a first type (e.g. symbols encoded with a first trellis code) and symbols of a second type (e.g. encoded with a second, more robust, trellis code), without storing path indicators along a trellis for symbols of the first type. In this way, limited memory may be used to store path indicators along the trellis for symbols of the second type. This allows for more accurate decoding of the symbols of the second type. For transitions from symbols of the second type to symbols of the first type, states of the trellis decoder may be stored. In this way, paths may be traced back along the trellis for trellis decoding, without the path indicators for the symbols of the first type.

Abstract: A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated within a video-processing portion of a personal digital assistant is analyzed. As reduced activity is identified, power conservation modes are implemented. In a normal mode of operation, a clock signal generated through an external oscillator is provided to a phase locked loop (PLL). An output clock signal from the PLL is then provided to several dividers to generate system clock signals. In a reduced mode of operation, the output clock from the external oscillator is provided to a divider, bypassing the PLL. Video processing components then use clock signals based on the external oscillator. In a suspend mode, both the PLL and the external oscillator are disabled.

Abstract: The system for updating a clock in an electronic device, such as a personal computer, has a receiver system having an input for receiving a real time signal and having an output on which is provided digital information representative of the real time signal. An extraction module is operatively coupled to the receiver system, the extraction module extracting at least a current time value from the display data. An update module is operatively coupled to the extraction module, the update module updating the clock in the computer when the current time value of the digital information differs from a current value of the clock in the computer. In one embodiment a validating unit is operatively coupled between the extraction module and the update module. The validating unit compares channel identification data derived from the display data to time zone data in the computer, the time zone data being indicative of a time zone in which the computer is currently located.

Abstract: A system and method for handling errors is provided. Errors related to the processing and storage of inverse discrete cosine transform (IDCT) image data cause hardware to become stalled. Stalled hardware may result in multiple image frames being dropped or lost during video playback. To avoid the stalling of hardware, the hardware is used to analyze the data being processed. Data being stored may be analyzed to determine if any error-characteristics, such as overflow or underflow, are present in the storing of the data. The data is manipulated to avoid stalling due to the error-characteristics.

Abstract: A program information player automatically skips over any intermediate channel changes as a result of interrupting a prior recording of a selected program. The program information player includes a program sequence playback information generator. The program sequence playback information generator analyzes selected program identifier information and recorded program history log information and, in response, generates program sequence playback information without user intervention. The program sequence playback information includes a sequence of time stamp information associated with the selected program identifier information. According to one embodiment, the program sequence playback information directs memory to play back the selected program corresponding to the selected program identifier information by, for example, skipping over any intermediate channel changes. For example, the program sequence playback information may represent a read pointer in memory during playback.

Abstract: Carrier phase recovery employs a single-axis blind cost criterion from the Bussgang class of functions, and its stochastic gradient, to generate a carrier phase error used to adjust a received and demodulated signal to near baseband. For one implementation, the estimate is derived in accordance with a Single-Axis Constant Modulus (SA-CM) criterion and its stochastic gradient via a SA-CM algorithm (SA-CMA). The carrier phase error is then used to adjust the carrier frequency and phase of the received and demodulated signal toward the frequency and phase of the carrier used to modulate the transmitted symbols, driving the carrier phase error to zero. The values used for the phase recovery may be either i) an IIR filtered signal, ii) a processed signal (e.g., decisions for the signal symbols), or iii) an equalized and processed signal.

Abstract: A system and methods are provided for presenting processed audio data and processed video data to corresponding outputs in a synchronized manner. Video and audio data from a multimedia stream are received by a processing system. The video data is processed through a video processor. The audio data is processed through an audio processor. Processed audio data is stored in memory through a VIP data port. A bus-master engine is used to delay a transfer of the audio data from memory to an output port. The delay is determined so as to allow video data enough time to be processed and output in synchronous with the audio data transferred from memory. Once the delay has been overcome, the bus-master asserts a trigger in the data bus to initiate the transfer from memory to the output port.

Abstract: A tool changer comprising a master module and a tool module includes a rapid-connect communication bus between the master and tool modules. A unique tool identification number, along with other tool-related information, may be transmitted from the tool module to the master module within about 250 msec of the master and tool modules coupling together. The master module includes a robotic system communications network node connected to the rapid-connect communication bus, and operative to transmit data between the tool and the network via the communication bus. The need for a separate network node in the tool module is obviated, reducing cost and reducing the start-up time required to initialize such a network node upon connecting to a new tool. The rapid-connect communication bus may be a serial bus.

Abstract: A single-axis receiver processing, for example, complex vestigial sideband modulated signals with an equalizer with forward and feedback filters. Forward and feedback filters have parameters that are initialized and adapted to steady state operation. Adaptive equalization employs linear predictive filtering and error term generation based on various cost criteria. Adaptive equalization includes recursive update of parameters for forward and feedback filtering as operation changes between linear and decision-feedback equalization of either single or multi-channel signals. An adaptive, linear predictive filter generates real-valued parameters that are employed to set the parameters of the feedback filter. In an initialization mode, filter parameters are set via a linear prediction filter to approximate the inverse of the channel's impulse/frequency response and a constant modulus error term for adaptation of the filter parameters.

Abstract: A system and methods are shown for performing a hardware performance analysis of graphics hardware and an application program. An application program generates a set of function calls. The function calls are translated to a native command set. The native command set is stored within a database. Software simulations and hardware emulations are used to compare the stored native command set data to a hardware architectural description of the graphics hardware. Data collected from the simulations are used to provide a performance model from which the performance of a graphics hardware executing commands for the application program can be determined.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: A method and apparatus for reducing instruction dependencies in extended SSA form instructions includes examining a first instruction of a worklist, wherein the worklist contains instructions in the extended SSA form that have a source, a previous link and a write mask and further produce an output. The method and apparatus further includes examining at least one second instruction of the worklist, wherein at least one second instruction is a source of the first instruction. Lastly, the method and apparatus includes translating the plurality of instructions in the worklist into a second plurality of instructions in the extended SSA form where the second plurality of instructions contains less instruction dependencies such as previous links.

Abstract: A method and apparatus for interpolating pixel parameters based on the plurality of vertex values includes operating first and a setup mode and a calculation mode. The method and apparatus includes, while in a setup mode, generating a plurality of differential geometric values based on the plurality of vertex values, wherein the differential geometric values are independent of a parameter slope between the plurality of vertex values. While in a calculation mode, a first geometric value and second geometric value are determined based on a pixel value, a plurality of vertex values and the differential geometric values. A pixel value is determined for each of the plurality of pixels based on the vertex parameter value, the first geometric value and the second geometric value. Thereupon, pixel parameters may be interpolated on a per-pixel basis reusing the differential geometric values.