Abstract: A process for providing a zirconium basic sulfate includes providing a zirconium oxychloride solution, and then dialyzing the solution against a liquid selected from water and an aqueous solution across at least one anion exchange membrane to provide a dialyzate and diffusate. The dialyzate includes at least 90 percent of the zirconium ions of the zirconium oxychloride chloride solution and has a total acidity that is lower than the original zirconium oxychloride solution. A precipitate including zirconium basic sulfate may be formed from at least a portion of the diffusate. The zirconium oxychloride solution may be provided, for example, by dissolving zirconium tetrachloride in one of water and a hydrochloric acid solution. A material including zirconium basic sulfate produced by the process of the invention also is disclosed.

Abstract: A method and apparatus for protecting access to audio and/or video data is accomplished when data is received, where the data may be audio data and/or video data. Having received the data, it is interpreted to determine whether an embedded data access parameter is active. If so, an indication of the particular type of data access is generated. The data access parameter may control access to the data as at least one of: copy restrictions, viewing restrictions, and/or use restrictions. The indication is subsequently provided to a computer system such that unauthorized accessing, including unauthorized copying, of the video and/or audio data is prohibited.

Abstract: A method and apparatus for controlling and caching memory read operations is presented. A memory structure is used to store data for read operations in a manner that allows the data to be reused in order to respond to similar subsequent memory accesses. Circuitry is included that determines if data corresponding to read requests is currently buffered in the memory structure. If it is, no additional memory accesses over a bus are required to respond to the read request. If the data is not currently buffered, a read request is issued over the bus, and when the data is returned in response to the read request, it is placed in the memory structure for responding to the read request and possibly for responding to additional subsequent read requests.

Abstract: An austenitic stainless steel comprising, by weight, 17 to 23% chromium, 19 to 23% nickel, 1 to 6% molybdenum. The addition of molybdenum to the iron-base alloys of the invention increases their resistance to corrosion. The austenitic stainless steel may consisting essentially of, by weight, 17 to 23% chromium, 19 to 23% nickel, 1 to 6% molybdenum, 0 to 0.1% carbon, 0 to 1.5% manganese, 0 to 0.05% phosphorus, 0 to 0.02% sulfur, 0 to 1.0% silicon, 0.15 to 0.6% titanium, 0.15 to 0.6% aluminum, 0 to 0.75% copper, iron, and incidental impurities. Austenitic stainless steels according to the present invention exhibit enhanced resistance corrosion by salt at a broad temperature range up to at least 1500° F. Thus, the stainless steel of the present invention would find broad application as, for example, automotive components and, more particularly, as automotive exhaust system components and flexible connectors, as well as in other applications in which corrosion resistance is desired.

Abstract: A method and apparatus for a multi-chip module that is testable and reconfigurable based on testing results is accomplished by a multi-chip module that includes a first circuit disposed on a first chip substrate, a second circuit disposed on second chip substrate, and an interconnecting substrate operably coupled to the first chip substrate and the second chip substrate. The interconnecting substrate connects the first circuit to the second circuit. The interconnecting substrate includes external connectors for accessing signals within the multi-chip module, which allow the multi-chip module to be fully tested. This testing may include isolating the first circuit and/or the second circuit by disabling other circuits in order to allow each of the circuits to be exercised without interference from other circuits. After testing the multi-chip module, configuration circuitry included on the multi-chip module may be used to reconfigure the multi-chip module based on results of the testing.

Abstract: A circuit and method for providing a reference voltage includes controlling a plurality of current sources which are passive during generation of a reference voltage within a suitable operating range, but which are active during corrective portions when the reference voltage varies outside of a suitable operating range. A plurality of sensing elements is used in connection with the current sources to provide feedback to maintain the reference voltage within a suitable operating range. In one embodiment, all circuit elements are made of a single gate oxide thickness.

Abstract: A method and apparatus for processing acoustic and/or gesture input commands by an entertainment device begins by detecting an acoustic initiation command and/or a gesture initiation command. The initiation command may be directed to a particular entertainment device, which may be a part of an entertainment center, or to the entire entertainment center. In addition, the initiation command corresponds to a particular operation of the entertainment device. Having detected the initiation command, the process proceeds by detecting an acoustic function command and/or a gesture function command, which is associated with the detected initiation command. The flnction command indicates the particular change desired for a corresponding parameter. Having detected the function command, it is interpreted to produce a signal for adjusting the parameter of the entertainment device.

Abstract: A video DAC uses a charge pump to maintain a constant peak to peak amplitude within power supply variations over process and temperature, rather than an external reference signal or a band gap reference. The charge pump performs calibration at full scale output during horizontal sync levels or vertical sync pulses.

Abstract: An apparatus and associated method for manipulating an electrode comprising a stub, an electrode, and a yoke. The stub is affixed to and protrudes from the electrode, and has a first opening. The yoke is sized to receive at least a portion of the stub, and has a second opening positioned for alignment with the first opening of the stub and receipt of a locking member extending through the first opening and the second opening. The apparatus may include a current conducting tube. The elongated yoke may extend around at least a portion of the stub to be removably pinned thereto. The current conducting tube may extend around the elongated yoke to be in electrical contact with the stub.

Abstract: A method and apparatus for performing scaling functions on a video signal is presented, where the scaling functions include a change in data rate of the signal. This is accomplished by performing the data rate conversion within a horizontal scaler of a video decoder. Filtering operations in the horizontal scaler are adjusted in order to take advantage of the data rate differential. Qualifier signals accompany portions of the video signal to indicate whether or not a particular portion of the signal is valid. These qualifiers are interpreted within the circuit to identify the portions that should be dropped, and the portions to be included in the output signal. In addition, registers within the horizontal scaler are used to store data corresponding to blanking regions within the input video signal, where data included in these blanking regions must be passed to the output signal in its entirety.

Abstract: A thread milling tool includes a proximal shank portion and a distal cutting portion. The cutting portion includes at least one thread milling tooth and at least one flute oriented helically, or spirally, about a rotational axis of the tool. The helix angle of the thread milling tool of at least 20°. The cutting portion may be configured to form internal or external threads in a workpiece as the cutting portion moves relative to the workpiece.

Abstract: A method of providing text data for display in a processor controlled apparatus comprised of storing data defining a text character in a memory, in packed monochrome bit map form, addressing the memory to read the text character data, providing the text character to a graphics processor circuit, performing a bitblt operation on each bit of the text character while providing a color attribute, and storing the packed text character having a color attribute for subsequent display.

Abstract: An input stage circuit and method provides voltage level conversion and overvoltage protection for an input stage circuit using a single gate oxide pass circuit and a single gate oxide voltage level shifting circuit. In one embodiment, the circuit and method includes receiving an input signal through the single gate oxide voltage pass circuit wherein the input signal can have a voltage level higher and lower than a first reference voltage for the voltage pass circuit. An output signal from the voltage pass circuit is provided to a single gate oxide voltage level shifting circuit that shifts a voltage level of the input signal from a first logic high level to a second lower logic high level when the input signal is above a reference voltage.

Abstract: A multistage A/D converter and conversion method includes generating a partial A/D bit result of a complete A/D result at a first bit/clock rate based on the received analog input signal and generating remaining A/D bits of the complete A/D result from the partial A/D bit result, at a second and slower bit/clock rate. Accordingly, the partial A/D result output from the first stage is used as input to determine remaining A/D bits to generate a complete A/D result.

Abstract: A method and apparatus for reducing memory bandwidth usage in video graphics texturing operations that utilizes caching of compressed textures is presented. Texture information for texturing operations is stored in a memory structure in a compressed format. When texture information is needed for a texturing operation, a local cache is first examined to determine if the texture information required for the texturing operation is present within the cache. If it is not, the texture information is retrieved from the memory in a compressed format and stored in the cache in the compressed format. The compressed texture information is then retrieved from the cache each time it is required for a texturing operation and decompressed prior to use in such texturing operations.

Abstract: A graphics display command list handler and method requests allocation of memory, such as system memory, in the form of a circular FIFO which stores the display command list as a memory display list (MDL), such as a host memory display list. A processor, such as a graphics processor, communicates a host memory display list read pointer to the host processor to facilitate display list signaling by the graphics processor. The host processor (or other processor) maintains a write pointer which points to a last host memory entry in the display list. The read pointer is maintained by the graphics processor and written back to the host processor.

Abstract: A method and apparatus for processing line anti-aliasing begins by walking a mathematical line based on the Bresenham technique. While walking the mathematical line at each pixel along the mathematical line- pixel coverage area is determined for each pixel of a set of pixels, where the set of pixels traverse a minor direction of the mathematical line. Note that for the mathematical line, the minor direction is the X direction when &Dgr;Y is greater than &Dgr;X and is in the Y direction when &Dgr;X is greater than &Dgr;Y. Once the coverage pixel coverage area of each pixel in the set of pixels has been determined, the intensity for each pixel in the set of pixels is determined. The intensity corresponds to the particular RGB value being generated for subsequent display.

Abstract: A method and apparatus for customized editing and/or censoring of video and/or audio signals begins when a signal and a plurality of editing parameters are received. The signal includes an audio and/or video signal, where each of the editing parameters corresponds to separate portions of the signal. The editing parameters may be embedded within the signal or provided in simulcast with the signal. While the signal is being processed, a selective editing circuit is monitoring the editing parameters. When an editing parameter indicates that the corresponding portion of the signal is to be edited, the selective editing circuit edits the corresponding portion based on the editing parameter, which may be provided by the content provider or the user. In addition, the editing parameter may indicate various levels of editing the signal.

Abstract: A method and apparatus for converting the color base of an image input layer include processing that begins by interpreting a conversion flag. The processing then continues by converting the color base of the image input layer from a first color base to a second color base when the conversion flag indicates a color base conversion. Note that a color base corresponds to standardized colorometries of video signals, color space of video signals, and/or any other displaying characteristics of video signals that are standardized or may be subsequently standardized. Further note that an image input layer corresponds to a display or portion thereof (e.g., a window or a picture in picture), wherein the display is capable of presenting images from multiple video and/or graphics data sources (e.g., a television signal and a computer application).

Abstract: A memory allocator employs a programmable and controllable switching circuit which switches multiple address buses and multiple data buses connected to the digital signal processing unit to differing banks of memory depending upon determined system requirement data, such as the amount of program memory and data memory necessary for a particular application. The memory space may be separate banks of memory incorporated into pools of memory if desired. The controllable switching circuit multiplexes the appropriate address bus and data bus to a given memory block or blocks which may be independent and can still be dedicated to specific application tasks. The memory banks are normal single address port and single data-port banks but are allowed to be connected to multiple data buses and address buses through the switching circuit. The switching circuit is sized to allow access to a subset of banks in a pool of banks associated with a given memory port. The digital signal processor is a multi-port device.