Abstract: A method and apparatus for recognizing and initializing second level peripherals on busses local to add-on cards. During startup, a personal computer receives an identifier from an add-on peripheral. A driver is executed that initializes the add-on peripheral, and determines whether any peripherals are attached to a secondary bus associated with the add-on peripheral. When a peripheral is identified on the secondary bus, information concerning the peripheral is added to a configuration file.

Abstract: A method and a computer for execution of the method. As part of executing a stream of instructions, a series of memory loads is issued from a computer CPU to a bus, some directed to well-behaved memory and some directed to non-well-behaved devices in I/O space. Computer addresses are stored of instructions of the stream that issued memory loads to the non-well-behaved memory, the storage form of the recording allowing determination of whether the memory load was to well-behaved memory or not-well-behaved memory without resolution of any memory address stored in the recording.

Abstract: A bank conflict detector compares at least a portion of a current address signal (i.e. an address signal generated by a request currently issued to main memory) with a corresponding portion of a to-be-issued memory address signal, to determine if a bank conflict exists. Specifically, in one embodiment, the bank conflict detector includes a number of exclusive OR gates that receive as inputs the two addresses to be compared, and generate an output (also called “XOR result”) that is compared with predetermined patterns to determine if a bank conflict exists. For example, if the bank conflict detector finds that the XOR result is 0 (zero) then the two addresses access the same bank. The bank conflict detector also the XOR result with patterns that are formed by a number of consecutive 1s in the least significant bits and a number of consecutive 0s in the most significant bits. If no match, then the bank conflict detector determines that no bank conflict exists.

Abstract: A method and apparatus for managing cache memory is described. The invention improves the efficiency of cache usage by monitoring parameters of multiple caches, for example, empty space in each cache or the number of cache misses of each cache, and selectively assigns elements of data or results to a particular cache based on the monitored parameters. Embodiments of the invention can track absolute values of the monitored parameters or can track values of the monitored parameters of one cache relative to one or more other caches. Embodiments of the invention may be scaled to accommodate larger numbers of caches at a particular cache level and may be implemented among multiple cache levels.

Abstract: A main memory scheduler includes a store, and stores therein requests for accessing main memory (such as a read request, a write request, or a refresh request). Normally, the main memory scheduler issues requests from the store to the main memory in an order different from the order in which the requests are received, for example, to avoid bank conflicts. In this example, the main memory scheduler issues a first request to a first memory bank that is not coincident with (and in case of dependent banks, not adjacent to) a second memory bank (that is being currently accessed) prior to issuing a second request to a memory bank that is coincident with the (or adjacent to) second memory bank. Moreover, the main memory scheduler issues a refresh request prior to issuing a read request or a write request even if the refresh request was most recently received, thereby to prioritize the refresh request ahead of read and write requests.

Abstract: A method and apparatus for processing data with improved concurrency that begins when a host processor an application identifies a memory block of a plurality of memory blocks based on memory block status. The application then provides a data block to the memory block. The data block includes data for processing, which includes application data and operating instructions, and a memory block status update command. A data retrieval command and a sequential updating command are provided to a processing entity by the application. The processing entity then retrieves the data block in accordance with the data retrieval command and processes the memory block status update command to produce an updated memory block status. Finally, the processing entity provides the updated memory block status to the application in accordance with the sequential updating command.

Abstract: A circuit for squaring an n-bit value includes a partial product bit generator which logically AND's a bit of the n-bit value having a weight 2k (k is an integer) with the same bit of weight 2k to generate a partial product bit of weight 22k. Another partial product bit generator receives and logically AND's a bit of the n-bit value of weight 2k and a bit of weight 2m (m is an integers) to generate a partial product bit of weight 2(k+m+1). The second partial product bit generator may be the only partial product bit generator in the squaring circuit to logically AND the bit of weight 2m and the bit of weight 2k. The circuit may also include other partial product bit generators. However, the required number of partial product bit generators is significantly reduced by about ½ compared to the conventional squaring circuit. The associated Wallace tree structure is simplified and made smaller because of the reduction in partial product bits.

Abstract: A prefetch buffer architecture includes a prefetch buffer connected to a memory unit via a global bus. A continue detect unit is also connected to the global bus via a global bus interface. The continue detect unit examines prefetched data words for a predetermined bit pattern indicating the possible presence of a “continue” command. The continue detect unit may use one or more comparator circuits to compare each prefetched data word with the predetermined bit pattern. Multiple comparator circuits can be used in parallel to simultaneously examine multiple data words. When the continue detect unit determines that a data word contains the predetermined bit pattern, indicating the likely presence of a “continue” command, the prefetch operation is suspended. The data word likely to contain the “continue” command is stored in the prefetch buffer until it is called by a decode unit, which decodes the continue command.

Abstract: The vacuum induction melting system of the present invention is designed to be operated in a continuous or semi-continuous manner for extended periods of time for increased efficiency, and makes it possible to easily and quickly remove the induction furnace from the melt chamber when it becomes necessary to replace and rebuild the furnace. The melting system includes a melt chamber which forms an airtight enclosure, with an induction furnace located within the melt chamber. A charging chamber is communicatively connected to the melt chamber adjacent its upper end. The charging chamber includes a door providing access to the interior of the charging chamber so that a charge of raw materials can be placed therein. An isolation valve is located between the melt chamber and the charging chamber and is movable between open and closed positions.

Abstract: A technique to increase the number of colors output by a passive color LCD display provides an increased number of grey levels for each pixel component. An M×N matrix pattern of pixel components is generated having a ratio of pixel components that are ON to the total number of pixel components to achieve a particular grey level on the passive color LCD screen, where M and N are greater or equal to two. The M×N matrix pattern is repeated for X frames, and at least one pixel component is ON in each frame. At the end of the Xth frame, the first matrix pattern for frame zero is repeated.

Abstract: A method and apparatus for both facilitating access to shared memory addresses over a common bus by a plurality of data processors includes detecting, by at least a first processor, that two access addresses are boundary addresses on either side of an address boundary. The method and apparatus locks the common bus in response to detecting the two access addresses. In addition, the method and apparatus locks the two detected addresses based on address probe inquiry data communicated by the first processor. Accordingly, at least one processor employs probe based bus lock and address lock control to facilitate efficient access to shared memory addresses. Preferably, each processor includes probe-based bus lock and address locking control. The method and apparatus provides a type of address locking with deterministic bus locking when needed.

Abstract: A method and apparatus for segregation of virtual address space in a computer system is provided. An embodiment of the invention provides compatibility of an emulated processor architecture with a native processor architecture. Address space for the emulated processor architecture is provided and segregated from other address space, such as address space designated for use by a native processor, where the native processor is the processor actually present in a computer system. An embodiment of the invention provides separate exception handlers to handle translation lookaside buffer (TLB) misses for each address space. An embodiment of the invention provides an address space tag associated with a virtual address to designate the address space to which that virtual address pertains.

Abstract: A connector that provides support for analog, digital, and high frequency analog signals is presented. The various connector positions of the connector are spaced in a manner that minimizes the surface area of the front face of the connector such that it can be accommodated within the bracket dimensions of an ATX bracket along with a DVI connector. The number of connector positions included in the connector allow for a large number of audio and video signals to be communicated to and from an expansion card included in a personal computer chassis.

Abstract: The present invention provides an apparatus and a method for variable size pages using fixed size TLB (Translation Lookaside Buffer) entries. In one embodiment, an apparatus for variable size pages using fixed size TLB entries includes a first TLB for fixed size pages and a second TLB for variable size pages. In particular, the second TLB stores fixed size TLB entries for variable size pages. Further, in one embodiment, an input of an OR device is connected to the second TLB to provide a cost-effective and efficient implementation for translating linear addresses to physical addresses using fixed size TLB entries stored in the second TLB.

Abstract: A cascaded output buffer stage and buffering method converts a voltage level of a received internal signal, such as a signal to be output (transmitted) from the cascaded output buffer stage, prior to outputting the received signal; selectively provides a variable reference voltage signal for a cascaded circuit element in the output buffer and also generates a floating well output signal for wells associated the cascaded upper buffer circuit elements. The cascaded output buffer stage is also, in one embodiment, a single gate oxide cascaded output buffer stage. In one embodiment, a voltage level shifting circuit is used along with a variable reference generating circuit that provides a variable reference voltage signal to cascaded output buffer circuits, and that also provides a floating well output signal to wells of the cascaded circuit. The voltage level shifting circuit and variable reference generating circuit is operatively coupled to a cascaded pull up circuit or cascaded pull down circuit as needed.

Abstract: A method and apparatus for accessing an external memory having a first width at at at a first data rate. The external data is reformatted to have a second predefined width larger than the first width. The data having the second predefined width is then provided at a second rate to one of several possible processing units.

Abstract: A system and method employs a single port digital video and/or audio capture circuit that is responsive to digitized uncompressed digital video and/or audio data and vertical blanking interval (VBI) data. In one embodiment, the single port capture circuit employs a parsing circuit that parses received VBI data along with any other received data such as video data and/or audio data and serves as a memory control signal generator that generates a VBI memory control signal and at least one of a video memory control signal and/or audio memory control signal to facilitate storage of the parsed VBI data, video data and audio data (if present) into predefined distinct locations within a memory, such as a frame buffer. A write FIFO memory receives the video data, VBI data, video memory address data and VBI memory address data (and audio information if present) as a storage hold prior to being stored in the frame buffer.

Abstract: A vacuum induction melting system includes a melt chamber which forms an airtight enclosure, with an induction furnace located within the melt chamber. A mold tunnel is connected to the melt chamber adjacent its lower end, with the mold tunnel including a pour opening which communicates with the melt chamber and through which molten metal poured from the furnace can enter the mold tunnel. A mold carriage is positioned within the mold tunnel for receiving and carrying one or more molds adapted for receiving molten metal. An isolation valve is located between the melt chamber and the mold tunnel for isolating the mold tunnel from the melt chamber to allow for removing the mold carriage from the mold tunnel for loading or unloading of molds thereon. A mold transport assembly is provided for moving the mold carriage from a pouring position within the mold tunnel to a loading position located outside of the mold tunnel.

Abstract: An extraneous voltage protection circuit and method transforms an overvoltage input signal or undervoltage input signal to a suitable voltage level for a protected circuit. An input voltage dependent variable reference voltage is used to protect overvoltage protection circuitry against unsuitable undervoltage conditions. In one embodiment, an overvoltage protection circuit, an undervoltage protection circuit, and an input voltage dependent variable reference voltage source is made of single gate oxide MOS devices.

Abstract: An integrated circuit and method utilizes a differential input receiver having a first input that receives an input signal. A reference voltage adjustment circuit produces a variable reference signal for the second input of a differential input receiver. A feedback path is provided from the output of the differential input receiver to an input of the reference voltage adjustment circuit. The reference voltage adjustment circuit dynamically varies the variable reference voltage signal to facilitate hysteresis. The variable reference voltage signal is lowered in the case of a high input signal, and raised in the case of a low input signal.