Abstract: One embodiment of a de-interlacing device has a decoder that extracts decoding motion vector data for use in de-interlacing of decompressed picture data, from an MPEG-2 type compressed data stream containing interlaced decompressed picture data made up of macroblock of data. The de-interlacing device also has a video rendering device for receiving the extracted decoding motion vector data from the decoder. The decoder has a determinator for determining whether the macroblock of data contains motion based on the decoding motion vector data and at least a subset of the block of data. The decoder generates motion vector based de-interlacing information containing information indicating whether each macroblock contains motion or no motion and if desired, a level of confidence that the referenced data is suitable for a particular method of de-interlacing.

Abstract: A buffer circuit utilizes a single gate oxide pre-buffer voltage level shifting circuit on, for example, an output buffer of an I/O pad, to accommodate different I/O pad supply voltages while maintaining normal operating voltages (degradation levels) across boundaries of single gate oxide devices that form the buffer. The single gate oxide output buffer can operate at several different supply voltages. A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having signal gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. A single gate oxide cross coupled active load is coupled to the multi-supply voltage level shifting circuit and provides suitable drive voltages to at least one of cascaded buffer transistors.

Abstract: A method and apparatus for improving the quality of video data when displayed on a display device that uses YUV output data to produce a display includes processing that begins by generating expanded RGB data from received RGB data. For example, the RGB data may be 8-bit data and the expanded data is generated by adding bits to it. The processing continues by generating RGB representative data from received YUV data. The RGB representative data is of the same format as the expanded RGB data and has a value range that includes and exceeds the normalized value range of the perceived RGB data. For example, the RGB representative data may have values less than zero and/or greater than 1, or normalized values outside of the zero to 1 range. The processing then continues by mixing the RGB representative data and the expanded RGB data to produce resulting RGB data, which has a similar format as both the expanded RGB data and the RGB representative data.

Abstract: A refining hearth. The refining hearth comprises an open vessel defining a first deep zone having a predetermined depth, a second deep zone having a predetermined depth, and a shallow zone intermediate the first deep zone and the second deep zone, wherein the shallow zone has a predetermined depth less that of the first deep zone and less than that of the second deep zone. A furnace for refining metal is also disclosed which employs a similarly constructed hearth. A method of refining metal is also disclosed. The method includes depositing molten metal in a first deep pool, passing the molten metal through a shallow pool having a depth less than the depth of the first deep pool, directing an energy source at the molten metal, and passing the molten metal into a second deep pool having a depth greater than the depth of the shallow pool.

Abstract: The present invention provides a two-port memory to connect a microprocessor bus to multiple peripherals. In one embodiment, an apparatus for an IO gateway subsystem of a microprocessor includes a bus of the microprocessor connected to a two-port memory, and a first peripheral connected to the two-port memory and a second peripheral connected to the two-port memory. In particular, the two-port memory communicates with the bus at a first clock rate, the two-port memory communicates with the first peripheral at a second clock rate, and the two-port memory communicates with the second peripheral at a third clock rate, in which the first clock rate, the second clock rate, and the third clock rate are asynchronous (e.g., the clocks have different phases, or the clocks have different frequencies).

Abstract: An integrated circuit chip has pads that are grouped into a number of groups, and also has functional modules that share, among each other, use of two or more groups of the pads (also called “external function” groups), for transferring signals (such as data signals and control signals) to or from external circuitry. Each functional module has one or more groups of terminals (also called “internal function” groups) for carrying these signals. The number I of internal functional groups is greater than another number E of external function groups. Therefore, at any given time, a number I-E internal function groups are uncoupled (i.e. not coupled to any pads of the integrated circuit chip). Couplings among groups are implemented independent of each other in a crossbar switch having I internal ports and E external ports, and at least I-E internal ports are always uncoupled.

Abstract: A method and apparatus for blending textures and other operands in a video graphics system using a single blend unit is accomplished through the following steps. A first set of control information is received. A first portion of the first set of control information is sued to select a first blend operand, which is preferably a texture in a graphics processing system. A second blend operand is selected based on a second portion of the first set of control information. The first and second blend operands are combined using an operation selected by a third portion of the first set of control information. The combination of the first and second blend operands produces a first combination result. A second set of control information is received, and a first portion of the second set of control information selects a third blend operand. The first combination result is then selected as a fourth blend operand using a second portion of the second set of control information.

Abstract: A squaring circuit includes an input terminal that carries a k-bit input value. The k-bit input value has left m-bit and right (k−m)-bit portions representing respective left and right hand values. A left hand squaring circuit receives the left hand m-bit portion and generates a first term bit group representing a square of the left hand value. A multiplier multiplies the left hand m-bit portion and the right hand (k−m)-bit portion to generate a second term bit group representing a product of the left and right hand values. A right hand squaring circuit generates a third term bit group representing a square of the right hand value. An adder adds the second term bit group with a concatenation of the first and third term bit groups and generate the square of the k-bit input value.

Abstract: A video encoding system combines the processing of image data and closed caption data in the formation of a raster television signal. By combining the processing of image data and closed caption data, a single discrete time oscillator (DTO) can be used to generate oscillation signals that are required for each process. In a preferred embodiment, the DTO generates the 500 kHz signal that is used as the “run in” clock for closed caption data, and also generates the subcarrier signal that is used for the modulation of the chrominance components of a composite video signal.

Abstract: An expansion card for a computer and a method for configuring the expansion card, where the expansion card includes a main card body, a daughter card, and a bracket. The main card body includes a coupling portion for coupling the expansion card to an expansion slot of the computer. The main card body further includes a connector area that is accessible from both the first and second face of the expansion card. The daughter card is coupled to the main card body on either he first or second face of the main card body, wherein the coupling configuration is determined based on the computer system chassis in which the expansion card is to be mounted The daughter card includes a connector that couples to the connector area of the main card body. The bracket is coupled to the main card body and the daughter card and facilitates mounting the expansion card in the computer chassis.

Abstract: The present invention provides an interpreter with reduced memory access and improved jump-through-register handling. In one embodiment, a method includes storing a handler for a bytecode in a cell of a predetermined size of a table, and generating an address of the handler for the bytecode using a shift and an ADD operation. In particular, the handler address is generated by adding a base address of the table and an offset into the table. In another embodiment, a method includes prefetching a target handler address for providing improved jump-through-register handling.

Abstract: A method and apparatus for a multi-state window is accomplished by presenting a multi-state window on a computer screen in various states. In a given state, or ghost state, the multi-state window for providing video and/or graphics is provided on screen in a translucent form. In the translucent form, a window overlapped by the multi-state window will be shown and remain in focus. When a user input is received in the overlapped portion, a multi-state window driver associated with the multi-state window will provide the input to the overlaid window, i.e., to its associated window driver or to the multi-state window driver depending upon the message type. If the user decides to activate the multi-state window, the multi-state window driver transforms the multi-state window from the translucent state to an in-focus state. When in the in-focus state, the user inputs are processed by the multi-state window driver and not provided to the overlaid window.

Abstract: An adder tree includes several partial product generators, each generating a bit of equal weight. An adder receives the bits and provides a carry bit to a logic unit. The logic unit propagates the carry bit to the next more significant column in response to a carry enable instruction. The logic unit outputs a bit that is independent of the carry bit in response to a lack of a carry enable instruction.

Abstract: A display controller in a graphics display system executes a primitive for displaying video images including multiple overlays. The primitive improves latency tolerance of the display controller and ensures seamless transitions between each frame of video images. The primitive of the present invention is executed on a display controller including a display processor. The primitive enables the display processor to process multiple control threads independently of each other. The threads execute a program to generate display signals for a frame of video image. Each of the threads executes a switch instruction when it completes processing of pixel data. The switch instruction causes the thread to determine if it is the last thread to be processed. When a thread is not the last thread, the thread is set to an inactive state. When a thread is the last thread, the primitive reactivates the multiple control threads to process pixel data for the next frame video image.

Abstract: A method and apparatus for a multi-state window is accomplished by presenting a multi-state window on a computer screen in various states. In a given state, or ghost state, the multi-state window is provided on screen in a translucent form. In the translucent form, a window overlapped by the multi-state window will be shown and remain in focus. When a user input is received in the overlapped portion, a multi-state window driver associated with the multi-state window will provide the input to the overlaid window, i.e., to its associated window driver. If the user decides to activate the multi-state window, the multi-state window driver transforms the multi-state window from the translucent state to an in-focus state. When in the in-focus state, the user inputs are processed by the multi-state window driver and not provided to the overlaid window.

Abstract: An adaptive video filter and method utilizes a first filter coupled to receive a composite video signal and generate a filter luminance output signal. An amplitude detector receives the filtered luminance output signal and generates an amplitude level to an amplitude threshold analyzer. The amplitude threshold analyzer has a selectable threshold to provide a selected range of false color filter coefficients to a programmable filter. The programmable filter may be part of a programmable false color filter bank and receives the luminance information and adaptively filters the luminance information based on the selected false color filter coefficients to facilitate false color compensation by attenuating false color frequency components in the filter means information.

Abstract: A method and apparatus for generating generic programming instructions using visual programming begins by providing a plurality of logical states that are interdependently related and include a set of programming options. When a programming option is selected, out of the set of programming options, for one of the plurality of logical states, the selected programming option is detected by a processing module. These programming options allow a user to change the characteristics of an image such as its color or brightness. Additionally, generic programming instructions corresponding to the selected programming option are provided to the user. The generic programming instructions are source code that is generated when a programming option is selected. With such a method and apparatus, generic programming instructions can be generated using visual programming that provides a set number of linked programming language blocks for use in video graphics processing.

Abstract: A deceleration circuit is operatively coupled to a first and second voltage to reduce noise on each of the voltage lines. For example, one voltage may be a supply voltage and the other voltage may be at a ground potential. The deceleration circuit may be coupled, for example, to each circuit that need not operate at a maximum or high operational speed within an integrated circuit that has other circuits that require high speed operation.

Abstract: A method and apparatus for storing and displaying multiple graphical images in a mixed video and graphics display is accomplished by determining an amount of memory sufficient to display a single graphics image in a subset of the display. Once the amount of memory required for a single image is determined, the pre-allocated portion of memory for graphics images is divided into an array. Graphics images are then rendered and stored within this array. One of the pre-rendered images is selected by a control block, wherein the selection is based on registers or parameters referenced by the control block. A display output engine fetches the selected one of the plurality of pre-rendered graphics images that is stored within the array and combines the selected graphics image with the video data stream to produce a display output stream. The display output stream is then fed to a display device that displays the graphics image.

Abstract: A method and apparatus for extending an on-chip processing device's access to memory are accomplished by depositing a processing circuit, memory, and configuration circuitry on a die. When the memory has sufficient digital storage capabilities for the processing circuit, the configuration circuitry directly couples an address bus and data bus between the memory and the processing device. When the memory does not have sufficient digital storage capabilities for the processing circuit, the configuration circuitry reconfigures the memory. In additional, the configuration circuitry extends the address bus to an external memory and combines the internal data bus with an external data bus. Configured in this manner, the processing device can access both the on-chip memory and the external memory as a single addressable memory, thereby increasing the memory available to the processing circuit.