Abstract: Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity check matrix can partitioned into rows and columns according to each of the sub-matrices of it, and each of those sub-matrices also includes corresponding rows and columns. For example, when performing bit node processing, the same columns of at 1 or more sub-matrices can be processed together (e.g., all 1st columns in 1 or more sub-matrices, all 2nd columns in 1 or more sub-matrices, etc.). Analogously, when performing check node processing, the same rows of 1 or more sub-matrices can be processed together (e.g., all 1st rows in 1 or more sub-matrices, all 2nd rows in 1 or more sub-matrices, etc.).

Abstract: A method and system for handling received out-of-order network data using generic buffers for non-posting TCP applications is disclosed. When incoming out-of-order data is received and there is no application buffer posted, a TCP data placement may notify a TCP reassembler to terminate a current generic buffer, allocate a new current generic buffer, and DMA the incoming data into the new current generic buffer. The TCP data placement may notify the TCP reassembler the starting TCP sequence number and the length of the new current generic buffer. Moreover, the TCP data placement may add entries into a TCP out-of-order table when the incoming data creates a new disjoint area. The TCP data placement may adjust an existing disjoint area to reflect any updates. When a TCP application allocates or posts a buffer, then the TCP reassembler may copy data from a linked list of generic buffers into posted buffers.

Abstract: A quantizer for quantization of a vector comprises a codevector generator that generates a set of candidate codevectors and a memory for storing an illegal space definition representing illegal vectors. The quantizer also includes a legal status tester that determines legal candidate codevectors among the set of candidate codevectors using the illegal space definition, and a codevector selector that determines a best legal candidate codevector among the one or more legal candidate codevectors. The vector includes parameters relating to a speech and/or audio signal, such as Line Spectral Frequencies (LSFs).

Abstract: A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.

Abstract: ZEB (zero excess bandwidth) modulation. The modulation rate of a signal is increased to the entirety of a communication channel's available bandwidth. Spectral zeroes at the edges of the available bandwidth now coincide with spectral zeroes at the edges of the Nyquist band and lead to ISI (intersymbol interference), which cannot be eliminated by equalization. Thus, in a ZEB system intersymbol interference (ISI) is intentionally allowed and dealt with by the known technique of TH (Tomlinson-Harashima) precoding. Comparison of conventional zero-ISI systems with ZEB systems, both exhibiting identical transmit spectra with finite spectral roll offs towards the edges of the available bandwidth, illustrate significant gains in channel throughput achievable by the ZEB systems. Similar gains can hardly be achieved by more sophisticated channel coding for zero-ISI systems. For ZEB systems an effective spectral shaping involving a simple infinite impulse response (IIR) of the overall channel is proposed.

Abstract: A universal serial bus (USB) dongle device includes a wireless telephony transceiver that receives an inbound RF signal and that generates inbound data based on the inbound RF signal and receives outbound data and that generates an outbound RF signal in response thereto. A USB plug is connectable to a host device. A USB controller circuit formats the inbound data in the USB format for communication to the host device and to recover the outbound data from outbound data received in the USB format from the host device. A millimeter wave interface includes a first millimeter wave transceiver coupled to the wireless transceiver and a second millimeter wave transceiver coupled to the USB controller circuit that wirelessly communicates the inbound data and the outbound data between the wireless telephony receiver and the USB controller circuit.

Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.

Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.

Abstract: Various example implementations are disclosed. According to one example, an integrated circuit may include a key extractor, a translation table block, and a memory assigner. The key extractor may be configured to receive data, extract key-related information from the data, and send the key-related information to a first memory device. The translation table block may be configured to update a mapping table based on a memory assigner assigning physical portions of the first memory device to each of a plurality of address types, receive an index from the first memory device in response to the key extractor sending the key-related information to the first memory device, and send a data request to a second memory device based on the received index, the data request identifying a physical portion of the second memory device.

Abstract: According to an example embodiment, an apparatus may include a non-Universal Serial Bus (non-USB) serial interface, a USB connector, a first protection circuit connected between a first data connection of the non-USB serial interface and a first data connection of the USB connector, a second protection circuit connected between a second data connection of the non-USB serial interface and a second data connection of the USB connector, a processor, and a detection circuit connected to the second data connection of the USB connector, the detection circuit configured to output a signal to the processor indicating an attachment or connection of a second non-USB serial interface to the USB connector.

Abstract: An integrated circuit containing multiple modules coupled to a pad via a multiplexer. The modules are selectively coupled to the pad by the multiplexer to provide integrated circuit function flexibility with a limited number of pads. A multiplexer select signal determines which module or clock circuit is coupled by the multiplexer. A common buffer may be coupled between the multiplexer and the pad to save substrate space. An analog circuit may be coupled to the pad to provide a signal path minimizing signal distortion. The integrated circuit's clock may be coupled via the multiplexer to an off-substrate circuit. Selective module coupling improves the integrated circuit's testing speed, may salvage an integrated circuit containing a malfunctioning module, and provides for signal loopback during testing.

Abstract: An active splitter circuit arrangement includes a first amplification module having a number of first input ports and first output ports. The first amplification module is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals, each substantially matching the input signal. Also included is a first gain control device having a number of gain input ports respectively coupled to the first output ports and a gain output port coupled to at least one of the first input ports. The first gain control device is configured to control a gain of the first amplification module. Next, a number of second amplification modules corresponding to the number of output signals has a number of second input ports respectively coupled to the first output ports.

Abstract: A system and method for processing information transport elements, such as ethernet packets, at interfaces to a forwarder. Modules that implement processing logic are allocated per interface and per direction (i.e., inbound or outbound). At any given interface, a series of modules would be used to process inbound packets; likewise, a set of modules would be used to process outbound packets. For inbound packets, the modules allocated for inbound processing are executed when the packet is received from the interface, before sending the packet on to the forwarder. For packets that are outbound from the forwarder, the modules allocated for outbound processing are applied when the packet is sent by the forwarder, prior to any other processing, e.g., queuing to hardware. To assign modules to different interfaces at a forwarder, a registration process is performed during the system start-up process, or dynamically at runtime.

Abstract: Methods and systems for processing an encoded video stream are disclosed. Aspects of the method may comprise generating a plurality of temporal or spatial prediction pixels based on mode information within the encoded video stream. A plurality of prediction errors may be generated from a plurality of quantized frequency coefficients generated from the encoded video stream. At least one current macroblock may be generated using the generated plurality of temporal or spatial prediction pixels based on the generated plurality of prediction errors. The encoded video stream may be symbol interpreted using context adaptive variable length coding and/or context adaptive binary arithmetic coding. The encoded video stream may be buffered prior to the symbol interpretation. The plurality of quantized frequency coefficients may be generated from the encoded video stream. If the encoded video stream comprises temporal prediction mode information, the plurality of temporal prediction pixels may be generated.

Abstract: A traffic prioritization system performs a coarse classification of upstream bursts at the physical interface of a headend communications device. The headend device monitors and controls communications with a plurality of remote communications devices throughout a widely distributed network, including the Internet. The traffic prioritization system includes a burst receiver that receives and sends the upstream bursts to a classifier. At an appropriate time, the classifier receives the upstream bursts and queries a priority lookup table (LUT) to determine a priority classification. The priority classification is used to separate the bursts into two or more priority levels. The higher priority level is used to designate services having a low tolerance for delay, such as telephony. Upon classification, the upstream bursts are forwarded to one of several priority queues. Each priority queue corresponds to at least one priority level.

Abstract: A method for estimating electrical length of a loop in a digital subscriber line (DSL) system begins by estimating an electrical length of a loop for each of a plurality signals based on a known power level of the plurality of signals, a known frequency for each of the plurality of signals, and a received power level for each of the plurality of signals. The method continues by processing the plurality of estimated electrical lengths in accordance with a function corresponding to characteristics of the loop to produce a determined electrical length.

Abstract: The invention refers to a video data processing system and a video data processing circuit, comprising at least two functional blocks of which at least a first functional block is programmable so that different functions can be provided by said first functional block.

Abstract: A method and system for increasing the efficiency of providing bandwidth for voice traffic to a data provider via wireless communication mediums is provided. This is generally accomplished by not transmitting any data during the silence periods and playing out background noise (i.e., comfort noise) at the other end, to obtain significant bandwidth savings.

Abstract: Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout.

Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.