Abstract: A system for detecting a key with key debounce including a circuit for detecting a key activation; a first counter coupled to the circuit and a clock for testing the key activation for a first user definable number of clock cycles; a key debounce buffer for storing a key index identifying the activated key, if the key activation is valid for the first user definable number of clock cycles; a second counter for testing the identified activated key for a first user definable number of hardware key scan cycles; and a key event buffer for storing a key activation event, if the key activation is valid for the first user definable number of hardware key scan cycles.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

Abstract: A minimal leakage power Standard Cell Library is provided. The minimal leakage power Standard Cell Library provides minimal leakage power cells with improved speed characteristics. The minimal leakage power Standard Cell Library includes cells from an existing Standard Cell Library and a set of minimal leakage power cells for a selected set of logic functions. The minimal leakage power Standard Cell Library is formed by identifying a set of logic functions. For each logic function in the identified set, a base case for an unfolded implementation of the logic function is determined. Widths for transistors in a transistor topology used in the unfolded implementation of the logic function are determined based on the non-linear leakage power characteristics for the transistor topology to achieve minimal leakage power. The determined widths are then assigned to the transistors and the minimal leakage cell is added to the library.

Abstract: A supervisory communications system (such as, a headend cable modem termination system) manages communications with a plurality of remote communications devices (such as, a cable modem). The supervisory system enables each of its physical channels to have multiple logical channels, with each logical channel having differing channel parameters or operating characteristics. As a result, different types of communication devices are permitted to coexist on the same physical spectrum. In other words, a communications device using, for example, spread spectrum modulation technologies require different operating characteristics than a communications device using, for example, time division multiplexing technologies.

Abstract: An integrated circuit (IC) package is provided. The IC package includes a substantially planar substrate having a plurality of contact pads on a first surface electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate, an IC die having a first surface mounted to the first surface of the substrate, and a heat sink assembly coupled to a second surface of the IC die and to a first contact pad on the first surface of the substrate to provide a thermal path from the IC die to the first surface of the substrate. The IC die has a plurality of I/O pads electrically connected to the plurality of contact pads on the first surface of the substrate. The IC die is mounted to the first surface of the substrate in a flip chip orientation.

Abstract: A second output transmission signal (“TX2”) added to a line driver is a scaled version of the main output transmission signal (“TX1”). TX2 is scaled from TX1 by a variable scale factor K. An adaptive hybrid circuit subtracts TX1 and TX2 from a line signal carrying both a line transmission signal and a line received signal (“RX”). A programmable impedance Ztune is coupled between the TX2 output of the line driver and the RX output of the adaptive hybrid circuit. A transmission echo in the output RX signal is measured. K and Ztune are then adaptively tuned to minimize the transmission echo. The hybrid in this case becomes a 4-port network, one port specifically added to adaptively cancel the transmission echo in the RX output of the adaptive hybrid circuit. Alternatively, the hybrid may be a 3-port hybrid including variable impedances to cancel the line transmission signal.

Abstract: A system and method for seamlessly reprogramming clock frequencies includes a phase locked loop (PLL) that generates CPU and double data rate (DDR) clocks. A crystal is used to generate a reference clock. The CPU clock and the reference clock are inputs to a first multiplexer, and the DDR clock and reference clock are inputs to a second multiplexer. In normal operation the multiplexers provide the CPU and DDR clock signal as outputs. To reprogram the clock frequencies and reset the PLL, (1) the reference clock signal is selected to be the output of both multiplexers, so the device is running on the internal reference clock. The mux switching is synchronized with the CPU and DDR clock signals. (2) The PLL is reprogrammed, its internal voltage-controlled oscillator is reset, and the PLL is restarted at the new desired frequency. (3) When the new PLL frequency output is stable, the multiplexers are switched back to the PLL-generated CPU and DDR clocks, synchronously with the reference clock signal.

Abstract: Methods for identifying devices may include receiving by one or more memory devices, one or more of a plurality of read memory device ID commands. The one or more memory devices may respond to the received one or more of the plurality of read memory device ID commands. The response may include identification information corresponding to the one or more memory devices. The one or more of a plurality of read memory device ID commands may correspond to one or more of a plurality of supported memory devices. At least one access protocol may be utilizing for performing reading, erasing, and/or writing to the one or more memory devices, if the response identifies the one or more memory devices as one of the one or more of the plurality of supported memory devices.

Abstract: A method of searching a signed codebook to quantize a vector includes weighting a shape codevector in a set of shape codevectors with a weighting function for a Weighted Mean Square Error (WMSE) criteria, to produce a weighted shape codevector. The method further includes correlating the weighted shape codevector with the vector to produce a weighted correlation term. The method also includes determining, based on a sign of the weighted correlation term, a preferred one of a positive and a negative signed codevector associated with the shape codevector. The method further includes determining whether one of the signed codevectors does not belong to an illegal space defining illegal vectors.

Abstract: An integrated circuit chip include a transmitter configured for transmitting an electromagnetic signal, a receiver configured for receiving an electromagnetic signal, and an amplifier operatively coupled to the receiver. The amplifier includes a plurality of variable-gain Gm-C filter stages connected in series and configured for selectively amplifying frequency components within a frequency bandwidth of the received electromagnetic signal.

Abstract: Methods for designing a filterless class-D amplifier and driver are described herein. In the exemplary embodiment, a feedback loop is used to stabilize the filterless class-D amplifier. A pulse width modulated (PWM) output signal is generated by adding a comparator input signal to a comparative signal, and comparing the sum to a peak voltage, which can be a peak value of the comparative signal. A limit of one PWM sample will be generated half per period of the comparative signal, resulting in lower dynamic switching noise and a decreased sensitivity to jitter noise than conventional filterless class-D amplifiers.

Abstract: A system and method that provide reduced latency in a video signal processing system. Various aspects of the present invention may comprise transmitting a first video information stream representative of a unit of video information. For example, the transmitted first video information stream may correspond to a video channel. A second video information stream representative of the unit of video information may be transmitted simultaneously with the first video information stream. The second video information stream may also, for example, correspond to the video channel. Various aspects of the present invention may comprise receiving a plurality of simultaneously transmitted video information streams. A video information stream of the plurality of received video information streams may be identified that, when processed, is expected to result in the lowest latency in presenting the unit of video information to the user. The identified video information stream may then be so processed.

Abstract: A wireless terminal displays its location and navigation information (map segment) on its display. The wireless terminal accesses a Global Positioning System (GPS) receiver of the wireless terminal to determine its location coordinates. The wireless terminal determines a maximum data size for navigation information to be downloaded. The wireless terminal sends a navigation information download request to a map server via a supporting wireless network infrastructure that includes the location coordinates and the maximum data size. The wireless terminal receives navigation information that has a data size no greater than the maximum data size and displays the navigation information on the display. The wireless terminal may display a map segment and an icon representing the wireless terminal at a location corresponding to the location coordinates of the wireless terminal with respect to the map segment. The wireless terminal may download a premises map from a premises map server.

Abstract: Improved apparatus for a radio communication network having mobile transceiver units in communication with base transceiver units. The radio communication network is adaptive in that in order to compensate for the wide range of operating conditions, a set of variable network parameters are adapted for communication between transceivers in the network. These parameters may, for example, define optimized communication on the network under current network conditions. Examples of such parameters may include, without limitation: packet size, data rate, type of modulation, type or degree of error correction coding and spread spectrum communication parameters.

Abstract: The present invention provides a transmitter architecture operable to cancel non-data-related direct current (DC) components therein. One method to cancel transmitter non-data-related DC offsets includes generating a baseband digital null signal. Then the digital null signal is converted to a pair of differential analog voltage null signals. The pair of differential analog voltage null signals may be converted to a pair of differential analog current null signals. The pair of differential analog current null signals is provided to a pair of matched impedances to generate a pair of voltage signals across the pair of matched impedances. A voltage offset results from comparing the pair of voltages generated across the pair of matched impedances. Then a current offset is determined based on the voltage offset.

Abstract: A method for enhancing the bit rate and/or margin at which quadrature amplitude modulation (QAM) communication is performed includes the steps of varying a spectral allocation and constellation size with which communication is performed, so as to define a combination of spectral allocation and constellation size at which the bit rate and/or margin are enhanced. The spectral allocation can be varied by varying a stop frequency thereof, while maintaining a substantially constant start frequency, so as to mitigate undesirable high frequency content of the bandwidth. Alternatively, both start and stop frequencies may be varied.

Abstract: Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Abstract: According to embodiments of the invention a multi-mode memory device is provided. The memory device includes at least one content-addressable memory (CAM). The memory device further includes a first match-in bus for receiving input into a first CAM of the at least one CAM, wherein the status of the match-in bus determines a operating mode of a plurality of operating modes of the first CAM, and a match-out bus for enabling the first CAM to be coupled to another CAM module and comprises match lines of a memory portion of the first CAM, wherein if the match-in bus is disabled, the first CAM is in a first mode, and if the match-in bus is enabled, the first CAM is in a second mode.

Abstract: A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell.

Abstract: A multiple processor device generates a control packet for at least one connectionless-based packet in partial accordance with a control packet format of the connection-based point-to-point link and partially not in accordance with the control packet format. For instance, the multiple processor device generates the control packet to include, in noncompliance with the control packet format, one or more of an indication that at least one connectionless-based packet is being transported, an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet, an indication of an amount of data included in the associated data packet, status of the at least one connectionless-based packet, and an error status indication.