Abstract: Methods and systems for decoding control channels using repetition redundancy may include generating enhanced soft bits by combining soft bits generated from the two GSM SACCH blocks. Combining may comprise averaging soft bits in one GSM SACCH block and corresponding soft bits from the other GSM SACCH block. Information in one GSM SACCH block may be repeated in the other GSM SACCH block. If repetition is detected, the enhanced soft bits may comprise enhanced soft bits for at least a portion of level 1 region and level 3 region of the GSM SACCH block. Otherwise, the generated enhanced soft bits may comprise enhanced soft bits for at least a portion of level 3 region of the GSM SACCH block.
Type:
Grant
Filed:
January 5, 2006
Date of Patent:
November 17, 2009
Assignee:
Broadcom Corporation
Inventors:
Huaiyu (Hanks) Zeng, Nelson Sollenberger, Arie Heiman
Abstract: Apparatus and methods for estimating transmission noise in a programming information signal. Channel noise power in binary phase shift keying (“BPSK”) modulated telecommunication may be estimated. Such a method may include receiving over the channel a reference signal and a data BPSK signal. The data BPSK signal may include the programming information. The method may include formulating a channel transfer function estimate for the channel based on the reference signal. The estimate may include a channel estimation error. The data BPSK signal may be equalized using the transfer function estimate. The data BPSK signal may include noise, which may be quantified in terms of power. The data BPSK signal noise power may be estimated in such a manner that is independent of the channel estimation error.
Abstract: A system and method is described that improves the intelligibility of a far-end telephone speech signal to a user of a telephony device in the presence of near-end background noise. As described herein, the system and method improves the intelligibility of the far-end telephone speech signal in a manner that does not require user input and that minimizes the distortion of the far-end telephone speech signal. The system is integrated with an acoustic echo canceller and shares information therewith.
Abstract: An RF integrated circuit (IC) includes a first IC port for coupling a first transmit signal in a first frequency band to at least one external device and a second IC port for coupling a second transmit signal in a second frequency band to the at least one external device. A transmitter module responds to outbound data to generate the first transmit signal in a first mode of operation and to generate the second transmit signal in a second mode of operation, wherein the transmitter module generates the first transmit signal and the second transmit signal in a selected one of a plurality of wireless telephony formats based on a control signal, and wherein the plurality of wireless telephony formats includes a code divisional multiple access format and at least one non-code division multiple access format.
Type:
Application
Filed:
May 12, 2008
Publication date:
November 12, 2009
Applicant:
Broadcom Corporation
Inventors:
Theodoros Georgantas, Konstantinos D. Vavelidis, Sofoklis Plevridis, Ilias Bouras
Abstract: A speech intelligibility enhancement (SIE) system and method is described that improves the intelligibility of a speech signal to be played back by an audio device when the audio device is located in an environment with loud acoustic background noise. In an embodiment, the audio device comprises a near-end telephony terminal and the speech signal comprises a speech signal received over a communication network from a far-end telephony terminal for playback at the near-end telephony terminal.
Abstract: Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.
Abstract: Presented herein is a system, method, and apparatus for firmware code-coverage in complex system on chip. A circuit for analyzing code coverage of firmware by test inputs comprises an input and a memory. The input receives an address from a code address bus. The memory stores recorded addresses from the code address bus. The memory comprises a plurality of memory locations, each of the memory locations mapped to a particular one of a corresponding plurality of addresses associated with the firmware. The contents of the memory location associated with the address received from the code address bus being incremented responsive to receipt of the address.
Type:
Grant
Filed:
January 27, 2004
Date of Patent:
November 10, 2009
Assignee:
Broadcom Corporation
Inventors:
Shiv Kumar Gupta, Ravi Ilpakurty, K. S. Narendranath
Abstract: A system and method for synchronizing translation lookaside buffer (TLB) access in a multithread processor is disclosed. When a first exception is found while searching the TLB, the exception is handled. While the exception is handled, thread processors are restricted from requesting the handling of any other exception.
Type:
Grant
Filed:
August 25, 2005
Date of Patent:
November 10, 2009
Assignee:
Broadcom Corporation
Inventors:
Kimming So, Jason Leonard, Gurvinder S. Sareen
Abstract: A Radio Frequency (RF) transceiver includes a first RF transceiver group, a second RF transceiver group, local oscillation circuitry, and calibration control circuitry. Each of the RF transceiver group has an RF transmitter and an RF receiver. The local oscillation circuitry selectively produces a local oscillation to the first RF transceiver group and to the second RF transceiver group. The calibration control circuitry is operable to initiate calibration operations including transmitter self calibration operations, first loopback calibration operations, and second loopback calibration operations. During loopback calibration operations, test signals produced by an RF transceiver group are looped back to an RF receiver of another RF transceiver group.
Abstract: A transmitter includes a first variable gain amplifier (VGA) and a second VGA coupled to an output of the first VGA. The first and second VGAs each comprise a plurality of parallel gain stages. Gains of the first and second VGAs are equal to the sum of the gains of the activated parallel amplifiers within each corresponding plurality of parallel amplifiers. Each parallel amplifier comprises a parallel differential amplifier controlled by a pair of switches to activate and deactivate the parallel differential amplifier. The gains of the first and second VGAs are increased by activating additional parallel amplifiers. The gains of the first and second VGAs are decreased by deactivating additional parallel amplifiers. The variable gains of the first and second VGAs provide an extended gain control with improved local oscillator (LO) leakage interference rejection.
Abstract: Aspects of a system for improving efficiency over power control for linear and class AB power amplifiers may include a current source circuit that enables determination of a bias current level for a PA circuit within an IC die based on an amplitude of an input modulation signal. The PA circuit may enable generation of an output signal based on a differential input signal and the input modulation signal to the current source circuit. A generated bias voltage may be applied to a transformer external to the IC die, but internal to an IC package containing the IC die and/or a circuit board containing the IC package. One or more amplifier bias voltage levels may be applied to the PA circuit wherein the amplifier bias voltage levels may be derived from the generated bias voltage level and/or the determined bias current level.
Abstract: An ESD protection circuit for a transistor having a drain and source coupled to high-speed signaling pins of an integrated circuit includes a first string of clamping elements and a second string of clamping elements. The first string of clamping elements has a collective capacitance less than the capacitance of a single clamping element. The first string of clamping elements is operably coupled to the drain and source of the transistor and conducts when a first polarity ESD voltage is applied to the high-speed pins. The second string of clamping elements has a collective capacitance less than the capacitance of one clamping element. The second string of clamping elements is operably coupled to the drain and source of the transistor and conducts when a second polarity ESD voltage is applied to the high speed signaling pins.
Abstract: An integrated circuit radio transceiver and method therefor includes capacitive loop filter with selectable capacitive elements that are operable to adjust a signal level provided to a voltage controlled oscillator to control a frequency of an output signal of the oscillator. A plurality of switches are controlled by logic to define a discharge mode, a charge mode and charge sharing mode in which a plurality of capacitive elements share charge while generating the input voltage to the oscillator.
Abstract: A method and system for bits and coding assignment utilizing Eigen beamforming with fixed rates for a closed loop WLAN is provided. Aspects of the method for communicating information in a communication system may comprise transmitting data via a plurality of radio frequency (RF) channels utilizing a plurality of transmitting antennas and receiving feedback information related to the plurality of RF channels. Bits may be assigned for transmission via at least one of the plurality of RF channels based on the feedback information. At least a portion of subsequent data having at least a first coding rate based on the assignment of bits may be transmitted via at least one of the plurality of RF channels. The method may also comprise receiving data via a plurality of RF channels utilizing a plurality of receiving antennas, and transmitting feedback information related to the plurality of RF channels.
Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.
Type:
Grant
Filed:
June 21, 2006
Date of Patent:
November 10, 2009
Assignee:
Broadcom Corporation
Inventors:
Ba-Zhong Shen, Tak K. Lee, Kelly Brian Cameron, Hau Thien Tran
Abstract: A method and system for increasing the efficiency of providing bandwidth for voice traffic to a data provider via wireless communication mediums is provided. This is generally accomplished by not transmitting any data during the silence periods and playing out background noise (i.e., comfort noise) at the other end, to obtain significant bandwidth savings.
Abstract: An offset cancellation scheme in which offset cancellation current is sourced into one differential branch of a driver circuit and sinked from the opposite differential branch. The source/sink arrangement allows for offset cancellation current to be introduced into the circuit, but the overall total average current remains substantially unchanged. When used in an I and Q mixer circuits, the offsets may be canceled without generating an I/Q imbalance in the I and Q mixers.
Abstract: The invention decreases phase distortion in a transmitter by balancing C load in the power amplifier input such that a PGA won't have phase distortion.
Abstract: Algebraic method to construct LDPC (Low Density Parity Check) codes with parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. A novel approach is presented by which identity sub-matrices undergo cyclic shifting, thereby generating CSI sub-matrices that are arranged forming a parity check matrix of an LDPC code. The parity check matrix of the LDPC code may correspond to a regular LDPC code, or the parity check matrix of the LDPC code may undergo further modification to transform it to that of an irregular LDPC code. The parity check matrix of the LDPC code may be partitioned into 2 sub-matrices such that one of these 2 sub-matrices is transformed to be a block dual diagonal matrix; the other of these 2 sub-matrices may be modified using a variety of means, including the density evolution approach, to ensure the desired bit and check degrees of the irregular LDPC code.
Type:
Grant
Filed:
December 1, 2005
Date of Patent:
November 10, 2009
Assignee:
Broadcom Corporation
Inventors:
Ba-Zhong Shen, Joseph Paul Lauer, Christopher J. Hansen, Kelly Brian Cameron
Abstract: A method for operating in a network that includes one or more of the following: assigning a respective active member address to each of a plurality of first slave nodes participating in a piconet; receiving a request to join the piconet; determining that no more different active member address are available in the piconet; determining that a second slave node supports extended addressing; and performing calculations as a function of the bandwidth requirements of the second slave node to determine whether to share an assigned active member address with the second slave node.