Abstract: A process for restoring an operational state of a portable handheld device is provided. The device may include multiple computing units and persistent storage. The operational state may be generated by a sequence of events. The operational state may receive signals corresponding to a plurality of event types. The process may include selecting an event type for storage, storing in the persistent storage events corresponding to the selected event type, receiving a signal indicating an interruption of operation, and transmitting the stored events to restore the device to the operational state.

Abstract: Provided is a method and system for estimating distortion in a communications channel including an adaptive equalizer. The method includes determining one or more adaptive filter coefficients associated with a signal passed through the equalizer. The method also includes estimating un-equalized channel distortion based upon the determined adaptive filter coefficients.

Abstract: A system for mitigating impairment in a communication system includes a delay block, a signal level block, a moving average window block, an impulse noise detection block, and a combiner. The delay block receives and delays each chip of a plurality of chips in a spreading interval. The signal level block determines a signal level of each chip of the plurality of chips in the spreading interval. The moving average window block determines a composite signal level for a chip window corresponding to the chip. The impulse noise detection block receives the signal level, receives the composite signal level, and produces an erasure indication for each chip of the plurality of chips of the corresponding chip window. The combiner erases chips of the plurality of chips of the spreading interval based upon the erasure indication.

Abstract: Aspects of a method and system for polar modulating QAM signals with discontinuous phase may include amplifying a signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain and an amplitude offset gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain, and a gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain. The setting of the coarse amplitude gain and/or said amplitude offset gain may be adjusted dynamically and/or adaptively. The signal may be generated by phase-modulation of a radio-frequency carrier. The combined gain of the plurality of amplifiers may be controlled based on a desired amplitude modulation. The plurality of amplifiers may be integrated within an integrated circuit (IC) or chip.

Abstract: The invention enables a gain adjustment in a receiver to improve signal quality.

Abstract: The motherboard comprises a CPU and a memory component; further at least one video data processing chip mounted to the motherboard wherein the video data processing chip is programmable; and further at least one additional memory component provided to store a software that is executable by the video data processing chip.

Abstract: The invention enables a compromise between DC offset rejection and image rejection through the use of a bandpass filter having a variable center frequency.

Abstract: One or more methods and systems of effectively transmitting voice and voice band data from one node to another are presented. In one embodiment, the system comprises an NTP time server generating absolute times to computing devices such as residential voice over internet protocol (VoIP) gateways. The NTP time server generates absolute times in response to NTP time requests made by one or more computing devices such as residential VoIP gateways. In one embodiment, the method comprises determining an adequate rate for requesting absolute times from an NTP server, making periodic requests to the NTP server, obtaining the absolute times from the NTP server, and generating an adjustment parameter for use by a computing device such as a residential VoIP gateway.

Abstract: A serial packet sync encoder is used to encode a serial packet sync datastream. In an embodiment, the serial packet sync datastream is made up of the packet sync vector and a unique preamble bit sequence that is preselected. In another embodiment, the serial packet sync datastream is made up of a non-unique bit sequence. A serial packet sync transmitter is used to transmit the serial packet sync datastream. A serial packet sync receiver is provided for receiving the serial packet sync datastream. In an embodiment, the serial packet sync transmitter and the serial packet sync receiver are shift registers. In this way, the serial packet sync datastream can be transmitted and received using only a single pin. The serial packet sync datastream is useful for providing an indication that an event, such as a grant arrival, has occurred. A preamble comparator is provided to compare the received serial packet sync datastream and the preselected preamble to determine if the two match.

Abstract: A method and apparatus is disclosed to convert a digital input signal to an analog output signal. A digital to analog converter (DAC) module converts the digital input signal to the analog output signal through segmentation. A primary sigma-delta modulator sigma-delta modulates the digital input signal to produce a primary digital segment and a primary quantization error. A primary sample delay delays the primary digital segment to produce a delayed primary digital segment. A primary decoder module decodes the delayed primary digital segment to produce a primary decoded digital signal. A primary scrambler scrambles the primary decoded digital signal to produce a primary scrambled digital signal. A primary DAC converts the primary scrambled digital signal from a digital representation to an analog representation to produce a primary analog segment. A secondary sigma-delta modulates the primary quantization error to produce a secondary digital segment.

Abstract: A circuit with dielectric thicknesses is presented that includes a low-pass filter including one or more semiconductor devices having a thick gate oxide layer, while further semiconductor devices of the circuit have thin gate oxide layers. The low-pass filter semiconductor device includes an N-type substrate, a P-type region formed on the N-type substrate, a thick gate oxide layer formed over the P-type region, a P+ gate electrode formed over the thick gate oxide layer and coupled to a first voltage supply line, and P+ pick-up terminals formed in the P-type region adjacent the gate electrode and coupled to a second voltage supply line. The low-pass filter semiconductor device acts as a capacitor, whereby a gate-to-substrate voltage is maintained at less than zero volts to maintain a stable control voltage for the circuit.

Abstract: A system and method are provided allowing for successive approximation analog to digital conversion. A first differential voltage is sampled and held during a first cycle. The first differential voltage is converted to a differential current. A second differential voltage is generated based on the differential current flowing through parallel-coupled respective first and second variable resistances. First and second portions of the second differential voltage are compared to produce a comparison result therefrom. Successive approximation is used to generate a signal based on the comparison result, the signal being an output signal and being used to control resistances of respective ones of the first and second variable resistances during subsequent cycles.

Abstract: A wireless communication system includes an access point and first and second stations. The first station transmits a first message that includes an address of a second station as a destination address and an address of the first station as a source address. The access point forwards the message including the address of the second station address as the destination address and the address of the first station as the source address. The second station receives the message from the first station during a first time interval and receives the first message from the access point during a second time interval. The second station processes the duplicate received message to produce inbound data.

Abstract: A wireless communication device includes a first receiver section and a second receiver section. The first receiver section receives a first probe signal from a first transceiver at time t1. The second receiver section receives a second probe signal from a second transceiver at time t2, wherein the first and second probe signals have substantially similar carrier frequencies. The first receiver section then receives a first signal from the first transceiver and the second receiver section receives a second signal from the second transceiver in accordance with an adjusted delay. The first and second signals have similar content and have substantially similar carrier frequencies. The adjust delay corresponds to a delta time that is substantially equal to a difference between the time t1 and the time t2 when the difference between the time t1 and the time t2 compares unfavorably to a delay threshold.

Abstract: A method begins by monitoring a plurality of channels within a frequency spectrum for transmission patterns. For a given channel of the plurality of channels, the method continues by determining whether a transmission pattern exists and, when the transmission pattern exists, determining at least one likely communication protocol of a plurality of communication protocols based on at least a portion of the transmission pattern. The method continues by determining an idle time of the given channel based on the likely communication protocol. The method continues by transmitting a signal via the given channel during the idle time, wherein the signal is in accordance with a second communication protocol.

Abstract: Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function call causes the cryptography accelerator to execute multiple cryptographic operations in a manner tailored for specific processing steps, such as steps during a handshake phase of a secured session. The techniques provide efficient use of hardware processing resources, data interfaces, and memory interfaces.

Abstract: A processing pipeline with a plurality of pipeline stages is described, with the processing pipeline comprising a front end and a back end. The processing pipeline's front end comprises an array for storing at least two condition bits, the condition bits being adapted for indicating respective conditions. The front end is adapted for resolving conditional branch instructions by accessing the array of condition bits whenever a conditional branch instruction occurs, the respective branch instruction being resolved in accordance with a corresponding condition bit. In another embodiment, the condition bits are combined with predicated execution of instructions, with the instruction's predicates being evaluated at the processing pipeline's back end.

Abstract: Successive interference canceling for CDMA. ICI may result from a signal's multi-path effects, or by filtering/suppression of some of the component energy of the signaling waveforms. Energy component attenuation destroys orthogonality of CDMA symbols thereby causing ICI. An ICF suppresses frequency domain portions(attenuates ingress), but also introduces ICI. Following the ICF, the signal is de-spread sliced, re-spread and convolved with the ICF echoes (except first tap echoes). Convolving re-spread hard decisions with delayed ICF taps is equivalent to partially re-modulating the first-pass hard decisions to efficiently “add-back-in” the signal energy which was blanked/subtracted by the ICF. Alternatively, parameter estimation de-rotates and re-rotates soft symbols and hard decisions, respectively, compensating for undesirable symbol rotation. The convolved signal is subtracted from a delayed version of the ICF output signal.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip uses window descriptors to describe logical surfaces, or windows, of graphics information to be displayed on the screen. The chip incorporates a unified memory architecture that provides a high level of system performance while conserving memory bandwidth and chip size. Video and graphics scaling capabilities as well as anti-flutter filtering capability are provided.

Abstract: Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in broadband applications. These two stages, (1) buffer stage (or data amplifier stage) and (2) cross-coupled differential pair stage, are both very fast operating stages. This design does not incur any increased loading to previous or subsequent stages in a device. In addition, there is no increase in the total amount of current that is required.