Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with an interrupt mapper for informing a plurality of processors about system-related functions for a plurality of channels. Using status registers containing interrupt status information for the plurality of channels, interrupt sources are specifically assigned to individual processors in the multiprocessor device so that the assigned processor can efficiently determine the source and priority of an interrupt by reading the register information.

Abstract: A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes at least one processing device, an IR processing function, and IR memory. The at least one processing device is operable to receive analog signals corresponding to a data block, to sample the analog signals to produce samples, to equalize the samples to produce soft decision bits corresponding to the data block, and to initiate IR operations. The IR processing function is operable to perform IR operations on the soft decision bits of the data block in an attempt to correctly decode the data block. The IR memory operably couples to the IR processing function, includes Type I IR memory adapted to store IR status information of the data block, and includes Type II IR memory adapted to store the data block.

Abstract: Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages is described. A die-up or die-down package includes a heat spreader cap defining a cavity, an IC die, and a leadframe. The leadframe includes a centrally located die attach pad, a plurality of leads, and a plurality of tie bars that couple the die attach pad to the leads. The IC die is mounted to the die attach pad. A planar rim portion of the cap that surrounds the cavity is coupled to the leadframe. The cap and the leadframe form an enclosure structure that substantially encloses the IC die, and shields EMI emanating from and radiating towards the IC die. The enclosure structure also dissipates heat generated by the IC die during operation.

Abstract: A wireless access point and multiple wireless terminals exchange utilization, status, mobility and reception characteristics. Each wireless terminal generates reception characteristics based on transmissions received from the wireless access point and from other devices in the network. In one operating mode, the characteristics gathered by the wireless devices are forwarded to the wireless access point, and, based on all received characteristics, the wireless access point selects its own transmission power for different types of the transmission. In another mode, all characteristics are exchanged between every wireless terminal and the access point so that each can independently or cooperatively make transmission power control decisions. In a further mode, the wireless access point adjusts protocol parameters based on an assessment of the characteristics received from the client devices.

Abstract: Certain embodiments for debugging mechanism for flow control based designs may comprise a debugging interface module between a transmitter and a receiver, all integrated on a chip. At least one debugging entity, which may be on the chip or off the chip, may indicate to the debugging interface module to initiate debug mode via command signals. In debug mode, the control signals between the transmitter and the receiver may be intercepted by the debugging interface module to halt normal data flow from the transmitter to the receiver. The debugging entity may then transmit data to the receiver, while the transmitter is disabled, or receive data transmitted by the transmitter, while the receiver is disabled. When the debugging entity indicates to the debugging interface module to end debug mode, normal data flow may continue, and the debugging interface module may appear transparent to the data flow.

Abstract: There is disclosed a receiver for receiving a multi-band DMT signal. The receiver includes a plurality of demodulators, each demodulator having a discrete Fourier transform and being provided to demodulate a respective one of a plurality of bands in the multi-band signal, the multi-band signal being modulated in an inverse discrete Fourier transform. A method of demodulating a multi-band signal is also provided.

Abstract: A method and apparatus for dynamic frequency selection in a wireless communication system or network includes processing that begins when an access point determines interference on a wireless channel that is being used by the access point. When the interference exceeds an interference threshold, the access point provides a request packet to affiliated stations being serviced by the access point for channel spectrum information. The processing continues as the affiliated stations generate the channel spectrum information regarding each of the wireless channels in the wireless communication network. The processing proceeds then as the affiliated stations provide the channel spectrum information to the access point via the current wireless channel. The access point interprets the channel spectrum information to determine a desired wireless channel of the plurality of wireless channels within the wireless communication network.

Abstract: Carrier detection applicable for SISO, MIMO, MISO, and SIMO communications. A novel approach is presented to perform carrier detection for a signal found in any of a wide variety of communication systems including single-input-multiple-output (SISO), multiple-input-multiple-output (MIMO), multiple-input-single-output (MISO) single-input-multiple-output (SISO), communication systems. This novel approach to performing carrier detection is more robust than those approaches existent in the art. By employing normalization with respect to power in determining a modified correlation function, there is less susceptibility to false detects. Also, this approach is quite robust to any circuitry DC offsets that may undesirably exist within a communication device that undergoes operational changes due to a variety of factors including environmental perturbations and/or changes in processing circuitry within the communication device (e.g., changes in gain control).

Abstract: A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.

Abstract: A baseband controller includes a microsequencer with special hardware resources circuitry and a configuration that supports real-time Bluetooth functionality for an upper limit of Bluetooth slave devices. The microsequencer includes a 72-bit correlator that may also be used as an accumulator, wherein the topology provides that the correlator can communicate with a 72-bit arithmetic logic unit that correspondingly enables the correlator to act as an accumulator. The microsequencer also includes a plurality of clocks and timers for facilitating Bluetooth timing functionality, and at least four registers for temporarily storing computational data, where each of the storage registers have different sizes for accommodating different-sized packets of computational data.

Abstract: Certain embodiments of the invention may be found in a method and system for single sideband mixing receiver architecture for improving signal quality in an RF communication system. An embodiment of the invention may mix a first input signal with a first local oscillator signal, via a first mixer, to generate a first mixed output signal. It may also mix a second input signal with a second local oscillator signal, via a second mixer, to generate a second mixed output signal. It may then generate a single sideband signal by adding the first mixed output signal and the second mixed output signal. The removal of one of two sidebands may reduce noise at the desired signal, since the removed sideband may have been at the same frequency as the desired signal.

Abstract: An analog front end. The analog front end comprises a converter configured to convert a differential input signal to a single-ended input signal, and convert a single-ended output signal to a differential output signal. And a transformer configured to couple the differential input signal from a twisted pair telephone line to the converter, and couple the differential output signal from the converter to the twisted pair telephone line.

Abstract: A power management scheme for a wireless communications device processor substantially implemented on a single CMOS integrated circuit is described. By incorporating controls for sleep and wake-up mode transitions in the processor's control logic, improved power savings with reduced latency is provided, obviating the need for hardware-focused solutions with elaborate signaling mechanisms. A fully integrated power management with staged wake-up operations controlled by the MAC solution consumes less power than the conventional wireless LAN solutions in standby mode.

Abstract: Described herein are systems and methods for determining data rate in a direct sequence spread spectrum system. The systems may include circuits or processors for receiving a signal that was transmitted at an unknown data rate and determining the value of the unknown data rate based on a sequence of bits that is generated from processing the signal according to a first data rate. The methods may include receiving a signal having an unknown data rate, processing the signal according to a first data rate, generating another signal that corresponds to a sequence of bits that result from the processing, and determining the value of the unknown data rate according to the sequence of bits.

Abstract: A power over Ethernet (PoE) powered device with power fallback states. A powered device can be powered using a primary local power source and a secondary PoE power source. To enable consistent behavior by the powered device, a controlled power fallback state can be defined that would ensure limited functionality in the powered device upon a failure of the primary local power source. For example, the limited functionality could include a communication channel to the switch, diagnostic circuitry, etc.

Abstract: Efficient memory management for hard disk drive (HDD) read channel. The memory management presented herein can be broadly applied to any interface in which data is provided from a first location to a second location. A number of buffer units are employed, arranged into a number of slices, in which data is selectively written so that the information can be provided to the memory management architecture at a first rate, stored in the memory management architecture, and then output from the memory management architecture at a second rate. This ensures appropriate interfacing of information while also performing appropriate rate adjustment. The data is partitioned into a number of portions, and each portion also includes multiple subsets. On a subset basis, information of a first portion is provided to a first slice's buffer units, and information of a second portion is provided to a second slice's buffer units.

Abstract: A system and method for communicating information relating to powered device (PD) power interruption and associated power sourcing equipment (PSE) fallback power. A PD can be powered using a primary local power source and a secondary power over Ethernet (PoE) power source. The PD communication can provide information that relates to PSE power delivery to the PD that is contingent upon detection of a failure occurring at the powered device.

Abstract: Apparatus and methods to receive and display digital television signals are described. In one embodiment, an apparatus to receive digital television signals comprises an antenna assembly (300) coupled to the signal processing circuitry and comprising a first antenna (310A) positioned to maximize reception in a first direction and a second antenna (310B) positioned to maximize reception in a second direction, different from the first direction, and a processor (340) coupled to the antenna assembly (300) and comprising a selection logic module (132) to select an antenna to receive a digital television signal for a specific channel, and a tuning logic module (134) to configure the antenna assembly to receive a signal via a selected antenna.

Abstract: A home network, in one embodiment including a home wiring system; a demarcation point unit in electrical communication with the home wiring system; and a home network module in electrical communication with the home wiring system. The home network module is adapted for connection to a home electronic device. The demarcation point unit passes data to and receives data from the home electronic device through the home network module.

Abstract: A system and method that support both progressive and interlaced format video transmission and display. The system utilizes de-interlacing techniques to convert input interlaced format video to progressive format video, and compress and vertically scale the progressive format video to communicate videos more efficiently in a progressive format. The system also supports interlaced and progressive displays, where after decompressing and vertically resealing the communicated compressed progressive format video, the video may be converted to interlaced format if the display supports interlaced format video. The system is capable of dynamically switching between the progressive and the interlaced format modes.