Abstract: A circuit for use in a wireless communication device includes a on-chip gyrating circuit that generates a motion parameter based on motion of the circuit. A GPS receiver receives a GPS signal and that generates GPS position data based on the GPS signal. A processing module processes the motion parameter to produce motion data and generates position information based on the GPS position data. A wireless telephone transceiver generates an outbound RF signal that includes outbound voice data and that generates voice inbound data from an inbound RF signal.

Abstract: A peripheral bus switch includes a virtual peripheral bus, a plurality of bridges, and a configurable host bridge. A first bridge operably couples on a first side to the virtual peripheral bus and supports connection on a second side to a peripheral bus fabric. A second bridge operably couples on a first side to the virtual peripheral bus and supports connection on a second side to the peripheral bus fabric. The configurable host bridge operably couples to the virtual peripheral bus, supports a host mode of operation in which it serves as a host bridge, and supports a device mode of operation in which it operates as a device.

Abstract: A method of handling packets includes inserting a stack-specific tag into a packet, then processing the packet in a stack of network switches in accordance with tag information in the stack-specific tag. The stack-specific tag is then removed from the packet.

Abstract: A method and system for decoding SACCH control channels in GSM-based systems with partial combining using weighted SNR may comprise combining least one weighted bit of a GSM slow associated control channel (SACCH) frame with at least one weighted bit of a subsequent GSM SACCH block based on burst signal to noise ratios (SNRs) of the GSM SACCH block and the subsequent GSM SACCH block. The burst SNR may be determined from a mid-amble of the GSM SACCH block and its subsequent GSM SACCH block. The burst SNRs of the GSM SACCH block may be translated to a corresponding plurality of scaling factors. At least a first weighting factor may be determined from the corresponding plurality of scaling factors. At least one weighted bit of the GSM SACCH block is determined utilizing the determined first weighting factor.

Abstract: Systems and methods that protect transport stream content are disclosed. The system may include a first module and a second module, the first module having a common interface. The second module is coupled to the first module via the common interface. In one embodiment, the first module is a set top box, and the second module is a conditional access card. In one example, the first module demodulates an incoming transport stream, copy protection encrypts the demodulated transport stream and passes the copy protection encrypted transport stream to the second module via the common interface. The second module copy protection decrypts the transport stream received from the first module, conditional access decrypts at least some of packets of the transport stream that were conditional access encrypted, copy protection encrypts the transport stream and passes the copy protection encrypted transport stream to the first module via the common interface.

Abstract: A single chip radio transceiver includes circuitry that enables detection of radar signals to enable the radio transceiver to halt communications in overlapping communication bands to avoid interference with the radar transmitting the radar pulses. One design goal, however, is to avoid false triggers that result from spurious tones and omissions and that further detects radar signals even in circumstances in which a radar pulse has been masked or eliminated by interference. Accordingly, the radar detection block includes circuitry for detecting and measuring the radar signals in the presence of such interference. More specifically, the radar detection block includes a moving average filter, a threshold comparison state machine, and radar detection logic within software that is executed by a processor for determining whether a radar signal is present.

Abstract: In wireless systems, a method and system for pre-equalization in a single weight (SW) single channel (SC) multiple-input multiple-output (MIMO) system are provided. A first receive antenna and at least one additional receive antenna may receive a plurality of SC communication signals transmitted from at least two transmit antennas. Estimates of the propagation channels between transmit and receive antennas may be performed concurrently and may be determined from baseband combined channel estimates. Channel weights may be determined to modify the signals received by the additional receive antennas. Pre-equalization weight parameters may be determined to modify subsequent signals transmitted from the transmit antennas. The pre-equalization weight parameters may be based on the propagation channel estimates and may be determined by LMS, RLS, DMI, or by minimizing a cost function. Closed loop transmit diversity may also be supported.

Abstract: A service aware flow control apparatus and method for multiple classes of data packets. A flow control sender includes a buffer of an ingress port per Class Group or Class of Service (COS). A counter per COS tracks an amount of buffer utilization per ingress port per COS, and each counter comprises an XOFF threshold level of congestion and an XON threshold. A controller detects, during transmission of the data packets, a counter associated with a buffer for a particular COS has risen to be greater than or equal to the XOFF threshold level of congestion. A flow control receiver ceases transmission of the data packets to the buffer for the particular COS experiencing congestion and allowing transmission of the data packets corresponding to other COS in the flow control sender.

Abstract: A table lookup indexing system for the transmission of data packets in a network switch. Data is received in an input port and is divided into two parts, an index portion and a bucket portion. The index portion selects a particular bucket and the combination of the index portion and bucket portion selects a specific entry in the table.

Abstract: A method of space-time and/or space-frequency block encoding begins by receiving at least two complex signals, wherein each of the at least two complex signals includes a real component and an imaginary component. The method continues, for each of the at least two complex signals, by generating a swapped complex signal, wherein each of at least two swapped complex signals includes a swapped real component and a swapped imaginary component, wherein the swapped real component corresponds to the imaginary component and wherein the swapped imaginary component corresponds to the real component. The method continues by encoding the at least two complex signals and the at least two swapped complex signals to produce space-time and/or space-frequency block encoded signals.

Abstract: A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Abstract: A dual-use PLL frequency synthesizer for use in a transceiver is capable of operating as a local oscillation generator in a receiving mode and as a transmitter in a transmitting mode. The PLL frequency synthesizer includes a digital processor, a Digital-to-Analog Converter (DAC), a low pass filter and a phase locked loop. The digital processor generates a digital signal, in which the digital signal is a modulated digital signal in the transmitting mode, and the digital signal is a reference digital signal in the receiving mode. The DAC converts the digital signal to an analog signal, and the low pass filter filters the analog signal to produce a filtered analog signal. The phase locked loop up-converts the filtered analog signal to an RF signal. In the transmitting mode, the RF signal is a modulated RF signal, and in the receiving mode, the RF signal is a reference RF signal.

Abstract: Aspects for secure access and communication of information in a distributed media network may include detecting when a legacy media peripheral is connected to a PC and/or a media processing system on the distributed media network. One or more identifiers associated with the legacy media peripheral may be established and utilized to facilitate communication of the legacy media peripheral over the distributed media network. At least one legacy media peripheral identifier and at least one identifier of a user utilizing the legacy media peripheral may be requested. The legacy media peripheral identifier may be a serial number of the legacy media peripheral, while the user identifier may be a user password and/or a user name. Media peripheral association software may be executed on the PC and/or the media processing system and utilized for media peripheral association and authentication in accordance with various embodiments of the invention.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: A system and method for meeting performance goals in an electronic system in an energy efficient manner. Various aspects of the present invention may comprise operating an electrical circuit at a current level of performance and a current level of energy efficiency by providing the electrical circuit with electrical power characterized by a current set of power characteristics (e.g., utilizing a power control module). The current level of performance may be determined (e.g., by a performance monitor) and compared to a desired level of performance (e.g., by the power control module). If the current level of performance is higher than the desired level of performance, then the electrical circuit may be operated at a next (e.g., lower) level of performance and a next (e.g., higher) level of energy efficiency by providing the electrical circuit with electrical power characterized by a next set of power characteristics.

Abstract: A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a plurality of predicate registers, and at least one execution unit configured to extract a plurality of bit fields from a source reservoir and to populate a plurality of destination lanes in response to a single instruction. In addition, the execution unit is configured to write supplied fill data into the source reservoir if the number of bits in the source reservoir is less than a predetermined number. In addition or alternatively, the system may include at least one execution unit configured to combine a plurality of bit fields from a plurality of source lanes into a continuous bit stream in response to a single instruction executable by the processor.

Abstract: A system and method for using an Ethernet physical layer device to identify cabling topologies. A power sourcing equipment (PSE) can power independent powered devices (PDs) using two sets of wire pairs in a single four-pair cable. Higher power PSEs can power a single PD using all four wire pairs in the cable. Conventional power over Ethernet (PoE) analog techniques (i.e., voltage, current, etc.) have a difficult time distinguishing where the wire pairs are going from the PSE. By using information (e.g., negotiated speed, link energy, distance diagnostic, etc.) generated by the physical layer device (PHY) subsystem, the PoE system can determine whether the two sets of wire pairs in a cable are powering a single PD or two independent PDs.

Abstract: High-resolution low-interconnect phase rotator. A signal may be generated having any desired phase (as determined by the step size employed). First and second control signals select a sector (e.g., the range from 0° to 360° is divided into a number of sectors) and a particular phase within that sector. Generally, this range from 0° to 360° is uniformly divided so that each sector is the same. However, if desired, there can alternatively be differences in the sizes of each of the sectors. The use of these two sets of controls signals (one for selecting the sector and one for selecting the particular phase within the sector) allows for very few control signals. N-channel metal oxide semiconductor field-effect transistor (N-MOSFET) based switches and differential pairs of transistors or alternatively p-channel metal oxide semiconductor field-effect transistor (P-MOSFET) based switches and differential pairs of transistors can be employed.

Abstract: Low power high-speed output driver. An array of switches (some of which are inverting switches whose connectivity is governed oppositely as the control signal provided to it) is implemented such that an input signal governs the connectivity of those switches. A resistor is coupled between the nodes interposed between the switches of the array, and an output signal is taken from the nodes at ends of the resistor. The high voltage level of such an output driver is truly the level of the power supply energizing the circuit (e.g., VDD) while still consuming relatively low power.

Abstract: A capacitive structure formed in an Integrated Circuit (IC) includes a plurality of capacitor node conductor pairs, each including a first node conductor having a base portion and a plurality of finger portions and a second node conductor having a base portion and a plurality of finger portions that are inter digitized with the plurality of finger portions of the first node conductor. Dielectric is horizontally disposed between the first node conductor and the second node conductor. At least one dielectric layer vertically separates adjacent metal layers, each dielectric layer including dielectric disposed between the adjacent metal layers, a plurality of first node vias vertically connecting finger portions of first node conductors of the adjacent metal layers, and a plurality of second node vias vertically connecting finger portions of the second node conductors of the adjacent metal layers.