Abstract: A handheld computing unit includes a processing module, a main memory interface, a baseband processing module, an RF section, input/output (I/O) interfaces, a bus structure, a handheld connection structure, and a ROM. The ROM includes a first section for storing a power on self test (POST) of basic input/output system (BIOS) and a second section for storing a boot loader of the BIOS. The boot loader includes a remote mode operating system boot loader and a docked mode operating system boot loader. The remote mode operating system boot loader is used to load a remote mode operating system when in a remote mode and the docked mode operating system boot loader is used to load a docked mode operating system when in a docked mode, which includes at least a portion of the remote mode operating system.

Abstract: An IC includes a microphone interface, a speaker interface, a baseband processing module, and RF section, a processing module, an on-chip to off-chip connector structure, and a digital audio switching module coupled to: provide the inbound voice signal from the processing module to the handheld speaker interface when the IC is in a remote mode; provide the outbound voice signal from the handheld microphone interface to the processing module when the IC is in the remote mode; provide the inbound voice signal from the processing module to the on-chip to off-chip connector structure when the IC is in a docked mode; and provide the outbound voice signal from the on-chip to off-chip connector structure to the processing module when the IC is in the docked mode.

Abstract: A power over Ethernet (PoE) power sourcing equipment (PSE) architecture for variable maximum power delivery. PoE PSE subsystems rely on some control to “turn on” a power field effect transistor (FET), which allows current to be transmitted to a powered device (PD). A hybrid approach is provided where an internal FET can be augmented with an external FET to provide an architecture that can be flexibly applied to applications with various space, cost and cooling limitations. The maximum delivered power can also be boosted with the addition of an external FET to the internal FET.

Abstract: An IC includes a processing module, on-chip memory, one or more block input/output (I/O) interfaces for coupling to one or more off-chip block I/O devices, one or more character I/O interfaces for coupling to one or more off-chip character I/O devices when active, a main memory interface for coupling to off-chip main memory, a baseband processing module, an RF section, a processing module interface, and an IC bus structure. The processing module interface couples the processing module to an off-chip connection structure, wherein, when a handheld computing unit that includes the IC is docked to an extended computing unit, the off-chip connection structure couples the handheld computing unit to the extended computing unit such that the IC is in a docked mode.

Abstract: An integrated circuit includes a first circuit and a plurality of first power supply lines for providing a first power to the first circuit. A first intra-chip clock interface generates a first clock signal on the first power supply lines. A plurality of second power supply lines are coupled to the plurality of first power supply lines and further couple a second power to the second circuit. A second intra-chip clock interface recovers the first clock signal from the second power supply lines. The second circuit operates based on the first clock signal.

Abstract: A plurality of inverters are arranged serially to form a ring oscillator and coupled to receive a reference clock signal. The reference clock signal is used to switch the inverters on and off so that not all of the inverters are on at a same time. The ring oscillator circuit is used as a divider circuit to divide the frequency of the reference clock signal to produce a local oscillator signal at a second frequency.

Abstract: A method and system for automatically trunking ports connecting network devices arranged in a stacked configuration is provided. The method includes sending a packet, from a sending network device to at least one other receiving network device, through each of a plurality of ports of the network device. The packet includes at least an identifier for identifying the sending network device. The receiving network device maintains a table identifying which ports are connected to a neighboring network device. The network device automatically trunks the ports which are connected to the same network device.

Abstract: A transmit signal generated by the baseband processor in a translational loop type RF transmitter is “pre-distorted” so as to counter act magnitude distortion and group delay variation imposed by a narrow PLL signal filter. The pre-distortion occurs in two steps: a magnitude equalizer in the baseband processor pre-distorts the amplitude of the transmit signal according to the inverse of the PLL signal filter magnitude response, and a group delay equalizer linearizes the phase response of the entire transmitter chain, i.e., pre-distorts the transmit signal such that the combined phase response of magnitude equalizer, group delay equalizer, and PLL signal filter is linear. With such pre-distortion, a loop filter is provided for with component values that define a relatively small bandwidth for the loop filter to filter spurious tones that result from an IF reference feedthrough to a voltage controlled oscillator of the translational loop.

Abstract: A method and device for transmitting a frame of a wireless communication begins by generating a preamble of the frame that includes a short training sequence and at least one long training sequence. The at least one long training sequence includes non-zero energy on each of a plurality of subcarriers except a DC subcarrier. The at least one long training sequence corresponds to the number of antennas and applicable wireless communication standards. A matrix is defined to represent the at least one long training sequence. The preamble is compatible with legacy and current standards. A channel is defined with a set of sub carriers to transmit the frame.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: Systems and methods are disclosed for detecting and mitigating temporary high-level impairments, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. The system includes a transmitter and a receiver. The transmitter is adapted to transmit at least one set of modulated signals. The receiver is adapted to receive the at least one set of modulated signals and mitigate temporary high-level impairment in the at least one set of modulated signals using at least one error vector received during the temporary high-level impairment.

Abstract: The invention relates to insertion and removal of MPA markers and RDMA CRCs in RDMA data streams, after determining the locations for these fields. An embodiment of the invention comprises a host interface, a transmit interface connected to the host interface, and a processor interface connected to both transmit and host interfaces. The host interface operates under the direction of commands received from the processor interface when processing inbound RDMA data. The host interface calculates the location of marker locations and removes the markers. The transmit interface operates under the direction of commands received from the processor interface when processing outbound RDMA data. The transmit interface calculates the positions in the outbound data where markers are to be inserted. The transmit interface them places the markers accordingly.

Abstract: A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning a local oscillation frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset. The circuitry further includes a multi-stage mixer that produces current signal outputs from each mixing stage to a subsequent stage thereby avoiding a need for intermediate transconductance and output stages to convert between current signals and voltage signals.

Abstract: Aspects of a method and system for compensating for using a transmitter to calibrate a receiver for channel equalization are provided. Various embodiments of the invention may be applicable wireless devices in TDM systems, Bluetooth, and/or WLAN applications, for example. Transmit tones may be generated by a transmitter PLL and the baseband response may be measured for each of the injected tones. The tones may be swept over a frequency range and a corresponding oscillator signal may be mixed with the received signal to determine the response of, for example, the receiver filters. Adjusting any of a plurality of receiver and/or transmitter parameters based on baseband measurements may provide appropriate channel compensation or calibration. Accordingly, the baseband circuitry may generate equalization signals, which may be utilized to adjust receiver and/or transmitter circuitry. This approach may be provide I/Q balancing and transmit filtering calibration after receiver calibration is completed.

Abstract: A circuit and method therefor provides programmable digital delay that is produced to introduces a delay in either an envelope or a phase signal path of an RF polar transmitter in order to eliminate the delay mismatch between the two paths. For two signal paths, a faster signal may be delayed by a digital processor or a slower signal may be transmitted early so that signals in the two signal paths arrive at a specified circuit node in synchronization. Timing shift may be implemented in either the envelope signal path or the phase signal path and may be used to reduce or increase the timing of a signal path.

Abstract: Low voltage LOGEN. LOGEN is a local oscillator generator. Two separately implemented dividers allow for relatively lower power dissipation while supporting multiple modes of operation within the communication device. Each of these two or more dividers has different phase noise characteristics. These at least two separately implemented dividers also allows for the supporting of at least two modes of operational within an apparatus. In certain applications (e.g., wireless applications), there is a need for relatively low phase noise characteristics therein, and the use of these at least two separately implemented dividers allows for the appropriate implementation of the relatively higher grade dividers in those areas that can benefit more there from.

Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo?N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.

Abstract: A cable infrastructure includes a plurality of cable modem circuits communicatively coupled to a cable network and associated with a corresponding one of a plurality of subscribers. Each of a plurality of telephones has both a POTS (Plain Old Telephone System) interface and a unique telephone number and associates with a corresponding one of the plurality of subscribers. Each of a plurality of interface circuits couples one of the plurality of cable modem circuits with a corresponding one of the plurality of telephones via the POTS interface. A head end system communicatively couples to the cable network, the public switched telephony network, and the Internet network and supports address mapping that enables communication exchanges between one of the plurality of telephones and an Internet telephony device. The address mapping also enables communication exchanges between telephones serviced by differing head ends via an Internet pathway that is independent of the public switched telephony network.

Abstract: Methods and systems for processing pixels within a decoded video stream are disclosed. Processed pixels may be received within the decoded video stream and may be buffered in a buffer at a first rate. The buffered received processed pixels may be transferred out of the buffer at a second rate, where the first rate is greater than said second rate. The buffering of the received processed pixels and the transferring of the buffered received processed pixels out of the buffer may be monitored to prevent an overrun of the buffer. The first rate of the buffering of the received processed pixels may be reduced to prevent the overrun of the buffer. The second rate of the transferring of the buffered received processed pixels out of the buffer may be monitored to prevent the overrun of the buffer. Amount of the buffered received processed pixels within the buffer may be determined.

Abstract: A network device for uniform distribution of non-unicast traffic, such as layer 2 broadcast, layer 2 multicast, unknown unicast and layer 3 multicast on a truch group. The network device includes at least one trunk group including a plurality of physical ports. The network device is connected to at least one other network device by a number of the plurality of physical ports. The network device also includes a table with a plurality of entries, wherein each entry is associated with the number of the plurality of physical ports on the network device. Each entry specifies if a packet should be transmitted on one of the plurality of physical ports. The network device further includes hashing means for hashing a predefined number of bits from predefined fields in the packet to select one entry in the table. The selected entry is used to identify a destination port. The network device also includes transmitting means for transmitting the packet to the destination port.