Abstract: Apparatus and methods for indicating the identity of a device for receiving and retransmitting programming information. The device, which may be a set-top box or suitable communication network receiver, may be configured to receive a broadcast signal from an antenna, which may be a satellite, a cable, an electronic communication network or any other suitable source. The programming information may be any type of audio or video data, or any other suitable type of data. The broadcast signal may have multiple channels that include the programming information. Each of the channels may include a distinct watermark. The device may splice between the channels to generate a signature that the device may embed in an output data stream that may be used to display or perform the programming information.

Abstract: A high speed data link includes transmitter equalization and (passive) receiver equalization to compensate for frequency distortion of the data link. In one embodiment, the transmitter equalization is performed with a de-emphasis circuit. The transmitter de-emphasis circuit pre-distorts an input signal to compensate for at least some of the frequency distortion in the data caused by the transmission line. The (passive) receive equalization circuit further compensates for the frequency distortion at the output of the transmission line to flatten the amplitude response of the output signal, and thereby reduce inter-symbol interference, improve media reach and improve the bit error rate (BER).

Abstract: Various aspects of a method and system for adaptive multi rate and measurements adaptation may include a processor that enables computation of at least one signal level measurement for at least one received signal. The processor may enable cancelling of interfering signals received in addition to the received signal based on processing of a received bit sequence using a first burst process operation (BP) in a first decoding algorithm that utilizes SAIC operations. The processor may also enable cancelling of noise signals received in addition to the received signal based on processing the received bit sequence using a second BP operation that utilizes redundancy and imposes a physical constraint during decoding. The processor may also enable adjustment of the computed at least one signal level measurement.

Abstract: A speech recognition device can include an audio signal receiver configured to receive audio signals from a speech source, a video signal receiver configured to receive video signals from the speech source, and a processing unit configured to process the audio signals and the video signals. In addition, the speech recognition device can include a conversion unit configured to convert the audio signals and the video signals to recognizable speech, and an implementation unit configured to implement a task based on the recognizable speech.

Abstract: According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude compensation circuit also includes a feedback circuit coupled to respective outputs of the first and second composite programmable buffers. According to this embodiment, the feedback circuit compares a first output amplitude of the first composite programmable buffer with a reference voltage and a second output amplitude of the second composite programmable buffer with the reference voltage and provides first and second control signals for adjusting the respective gains of the first and second composite programmable buffers so as to reduce respective differences between the first and second output amplitudes and the reference voltage.

Abstract: A radio receiver includes a single analog to digital converter, a 1st digital mixing module, and a 2nd digital mixing module. The single analog to digital converter is coupled to convert the filtered IF signal into a digital IF signal, which includes information regarding an in-phase component and a quadrature component of a modulated RF signal. The 1st and 2nd mixing modules each receive the digital IF signal and mix the digital IF signal with an in-phase and quadrature digital local oscillation to produce a 1st baseband signal component and a 2nd baseband signal component.

Abstract: A baseband processing module of a wireless terminal includes a Turbo decoding module. The Turbo decoding module decodes a Turbo code word to produce one or more Media Access Control (MAC) packet(s) carried by the turbo decode word. Each MAC packet includes a MAC packet header and the MAC packet payload, which carries one or more Radio Link Control (RLC) Packet Data Units (PDUs). The Turbo decoding module decodes the MAC packet header to determine boundaries of the PDUs carried in the MAC packet payload. The Turbo decoding module decodes RLC PDU headers and RLC PDU payloads of the RLC PDUs. The Turbo decoding module writes the decoded MAC packet header, the decoded RLC PDU headers, and the decoded RLC PDU payloads to memory in a word-aligned format. The Turbo decoding module may also operate in various other Turbo decoding modes.

Abstract: Decoding error correcting codes transmitted through multiple wire twisted pair cables with uneven noise on the wires. A novel approach is presented by which the metrics may be calculated for signals received over multi-wire (or alternatively referred to as multi-channel, and/or multi-path) communication channels to exploit an uneven distribution of noise among those wires for improved performance. In addition, this approach may also be performed in combination with employing an amplification factor to modify the metrics employed when performing ECC (Error Correcting Code) decoding. Moreover, when information is known concerning which 1 or more paths (e.g., wires) has an SNR that is different (e.g., lower in some cases) from the others, an even better adapted means of calculating the metrics associated with each of the paths (e.g., wires) may be employed to provide for improved performance with respect to iterative decoding processing of signals encoded using ECCs.

Abstract: Methods and associated systems provide secured data transmission over a data network. A security device provides security processing in the data path of a packet network. The device may include at least one network interface to send packets to and receive packets from a data network and at least one cryptographic engine for performing encryption, decryption and/or authentication operations. The device may be configured as an in-line security processor that processes packets that pass through the device as the packets are routed to/from the data network.

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The transmitter includes a plurality of current cells. Each cell is configurable for operating in different modes. The method includes determining a first probability associated with transmitting data at a particular symbolic level and determining a second probability associated with each cell being used during a transmission at the particular symbolic level. Next, one of the modes for each cell is selected in accordance with anticipated performance requirements. An average current of the transmitter is then calculated based upon the determined first and second probabilities and the selected modes.

Abstract: A network device for implementing high-rate greenfield transmission in a mixed mode frame structure. The network device is configured to transmit a mixed mode frame on two adjacent channels. The mixed mode frame comprises at least two backward compatible portions of a first frequency and a greenfield portion of a second frequency.

Abstract: Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders. A novel approach is presented by which the front end design of device capable to decode LDPC coded signals facilitates parallel decoding processing of the LDPC coded signal. The implementation of the front end memory management in conjunction with the implementation of a metric generator operate cooperatively lend themselves for very efficient parallel decoding processing of LDPC coded signals. There are several embodiments by which the front end memory management and the metric generator may be implemented to facilitate this parallel decoding processing of LDPC coded signals. This also allows for the decoding of variable code rate and/or variable modulation signals whose code rate and/or modulation varies as frequently as on a block by block basis (e.g., a block may include a group of symbols within a frame).

Abstract: A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting substantially different characteristics are employed in an overall scheme to link portable or mobile computing devices. The network accommodates real time voice transmission both through dedicated, scheduled bandwidth and through a packet-based routing within the confines and constraints of a data network. Conversion and call processing circuitry is also disclosed which enables access devices and personal computers to adapt voice information between analog voice stream and digital voice packet formats as proves necessary. Routing pathways include wireless spanning tree networks, wide area networks, telephone switching networks, internet, etc., in a manner virtually transparent to the user.

Abstract: In a RF communications system, aspects for single weight antenna system for HSDPA may comprise receiving HSDPA signals via a plurality of receive antennas and individually adjusting a phase of a portion of the received HSDPA signals via a single weight. The phase adjusted portion of the received HSDPA signals may be combined with at least one of the received HSDPA signals to generate combined HSDPA signals. At least one control signal may control the adjusting of the phase of the received HSDPA signals. Discrete phases may be communicated to adjust the phase of the portion of the received HSDPA signals, where the plurality of the discrete phases may range from zero radians to substantially 2? radians. Phase shift channel estimates may be generated during the identified time to determine the discrete phase. A desired phase may be generated from the phase shift channel estimates, and the single weight may be generated from the desired phase.

Abstract: Multiple-input-multiple-output (MIMO) timing recovery. A novel approach is presented to perform timing recovery when processing the multiple received signals within a MIMO communication device. This may be implemented for a singular received signal, or a plurality of received signal streams. In addition, this timing recovery may be performed in conjunction with carrier detection to provide more robust performance. Alternatively, indicia and/or signals corresponding to carrier detection of these signals may be provided to timing recovery functionality from carrier detection functionality external to the timing recovery functionality. Certain processing and analysis is performed on a modified correlation function that is generated using samples of moving windows that pass over symbols of a packet.

Abstract: A media access controller (MAC) is configured with a DOCSIS Header creator circuit. The DOCSIS header creator circuit is configured with logic for receiving a data packet and determining whether the received data packet has an existing packet header prepended thereto. The DOCSIS header creator circuit is further configured to determine if the length of the received data packet includes a cyclic redundancy code. Still further, the DOCSIS header creator circuit is configured to determine a packet header length field value for the received data packet. If the DOCSIS header creator circuit determines that a cyclic redundancy code needs to be included in with the received data packet, then the DOCSIS header creator circuit is able to generate a CRC flag. If the data packet needs to be encrypted, then the DOCSIS header creator circuit will generate an encryption flag if it is determined that the received data packet should be encrypted.

Abstract: A Radio Frequency (RF) transceiver includes a baseband processor, a receiver section, and a transmitter section. The receiver section communicatively couples to the baseband processor and includes a plurality of tuned RF circuits. The transmitter section communicatively couples to the baseband processor and includes a plurality of tuned RF circuits. In a calibration operation, the transmitter section applies a RF test signal to its plurality of tuned RF circuits. The baseband processor applies a plurality of tuning control settings to each the tuned RF circuit. The baseband processor, for each of the plurality of tuning control settings, measures an output of the tuned RF circuit. The baseband processor selects a tuning control setting for the tuned RF circuit based upon at least one measured output of the tuned RF circuit. Finally, the baseband processor is operable to apply a selected tuning control setting to the tuned RF circuit.

Abstract: The method and apparatus of the present invention provide for a configurable radio front end topology that allows selectable operation in a single balanced mode and in a double balanced mode of operation. Logic associated with a baseband processor determines whether to operate in a single or double balanced mode of operation and produces the mode control signal to control selective coupling of circuit components according to the specified mode. Switching circuitry is used to switch a Balun in and out of connectivity. Further, a pair of LO polarity blocks are operable to determine the polarity of a differential LO received by associated mixers according to whether a single balanced or double balanced mode is in use.

Abstract: A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting substantially different characteristics are employed in an overall scheme to link portable or mobile computing devices. The network accommodates real time voice transmission both through dedicated, scheduled bandwidth and through a packet-based routing within the confines and constraints of a data network. Conversion and call processing circuitry is also disclosed which enables access devices and personal computers to adapt voice information between analog voice stream and digital voice packet formats as proves necessary. Routing pathways include wireless spanning tree networks, wide area networks, telephone switching networks, internet, etc., in a manner virtually transparent to the user.

Abstract: Analog signal paths are utilized between a baseband processor and a radio front end to support high throughput communications for a multiple in multiple out radio transceiver that support communications over two or more antennas. Specifically, analog differential I and Q path communication signals are exchanged between a radio front end core and a baseband processor to maximize throughput capacity for high data rate signals. Along the same lines, the impedances of traces and the interface are matched to reduce I/Q imbalance.